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92 lines
4.3 KiB
92 lines
4.3 KiB
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# RandomX instruction set architecture
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RandomX VM is a complex instruction set computer ([CISC](https://en.wikipedia.org/wiki/Complex_instruction_set_computer)). All data are loaded and stored in little-endian byte order. Signed integer numbers are represented using [two's complement](https://en.wikipedia.org/wiki/Two%27s_complement). Floating point numbers are represented using the [IEEE 754 double precision format](https://en.wikipedia.org/wiki/Double-precision_floating-point_format).
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## Registers
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RandomX has 8 integer registers `r0`-`r7` (group R) and a total of 12 floating point registers split into 3 groups: `a0`-`a3` (group A), `f0`-`f3` (group F) and `e0`-`e3` (group E). Integer registers are 64 bits wide, while floating point registers are 128 bits wide and contain a pair of floating point numbers. The lower and upper half of floating point registers are not separately addressable.
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*Table 1: Addressable register groups*
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|index|R|A|F|E|F+E|
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|--|--|--|--|--|--|
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|0|`r0`|`a0`|`f0`|`e0`|`f0`|
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|1|`r1`|`a1`|`f1`|`e1`|`f1`|
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|2|`r2`|`a2`|`f2`|`e2`|`f2`|
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|3|`r3`|`a3`|`f3`|`e3`|`f3`|
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|4|`r4`||||`e0`|
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|5|`r5`||||`e1`|
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|6|`r6`||||`e2`|
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|7|`r7`||||`e3`|
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Besides the directly addressable registers above, there is a 2-bit `fprc` register for rounding control, which is an implicit destination register of the `CFROUND` instruction, and two architectural 32-bit registers `ma` and `mx`, which are not accessible to any instruction.
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Integer registers `r0`-`r7` can be the source or the destination operands of integer instructions or may be used as address registers for loading the source operand from the memory (scratchpad).
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Floating point registers `a0`-`a3` are read-only and may not be written to except at the moment a program is loaded into the VM. They can be the source operand of any floating point instruction. The value of these registers is restricted to the interval `[1, 4294967296)`.
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Floating point registers `f0`-`f3` are the *additive* registers, which can be the destination of floating point addition and subtraction instructions. The absolute value of these registers will not exceed `1.0e+12`.
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Floating point registers `e0`-`e3` are the *multiplicative* registers, which can be the destination of floating point multiplication, division and square root instructions. Their value is always positive.
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## Instruction encoding
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Each instruction word is 64 bits long and has the following format:
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### opcode
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There are 256 opcodes, which are distributed between 32 distinct instructions. Each instruction can be encoded using multiple opcodes (the number of opcodes specifies the frequency of the instruction in a random program).
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*Table 2: Instruction groups*
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|group|# instructions|# opcodes||
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|---------|-----------------|----|-|
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|integer |19|137|53.5%|
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|floating point |9|94|36.7%|
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|other |4|25|9.8%|
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||**32**|**256**|**100%**
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Full description of all instructions: [isa-ops.md](isa-ops.md).
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### dst
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Destination register. Only bits 0-1 (register groups A, F, E) or 0-2 (groups R, F+E) are used to encode a register according to Table 1.
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### src
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The `src` flag encodes a source operand register according to Table 1 (only bits 0-1 or 0-2 are used).
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Immediate value `imm32` is used as the source operand in cases when `dst` and `src` encode the same register.
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For register-memory instructions, the source operand determines the `address_base` value for calculating the memory address (see below).
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### mod
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The `mod` flag is encoded as:
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*Table 3: mod flag encoding*
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|`mod`|description|
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|----|--------|
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|0-1|`mod.mem` flag|
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|2-4|`mod.cond` flag|
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|5-7|Reserved|
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The `mod.mem` flag determines the address mask when reading from or writing to memory:
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*Table 3: memory address mask*
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|`mod.mem`|`address_mask`|(scratchpad level)|
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|---------|-|---|
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|0|262136|(L2)|
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|1-3|16376|(L1)|
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Table 3 applies to all memory accesses except for cases when the source operand is an immediate value. In that case, `address_mask` is equal to 2097144 (L3).
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The address for reading/writing is calculated by applying bitwise AND operation to `address_base` and `address_mask`.
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The `mod.cond` flag is used only by the `COND` instruction to select a condition to be tested.
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### imm32
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A 32-bit immediate value that can be used as the source operand. The immediate value is sign-extended to 64 bits unless specified otherwise.
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