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432 lines
13 KiB
432 lines
13 KiB
#ifndef VARIANT4_RANDOM_MATH_H
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#define VARIANT4_RANDOM_MATH_H
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// Register size can be configured to either 32 bit (uint32_t) or 64 bit (uint64_t)
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typedef uint32_t v4_reg;
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enum V4_Settings
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{
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// Generate code with minimal theoretical latency = 45 cycles, which is equivalent to 15 multiplications
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TOTAL_LATENCY = 15 * 3,
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// Always generate at least 60 instructions
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NUM_INSTRUCTIONS = 60,
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// Always generate at least 60 instructions
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NUM_INSTRUCTIONS_MIN = 60,
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// Never generate more than 70 instructions (final RET instruction doesn't count here)
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NUM_INSTRUCTIONS_MAX = 70,
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// Available ALUs for MUL
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// Modern CPUs typically have only 1 ALU which can do multiplications
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ALU_COUNT_MUL = 1,
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// Total available ALUs
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// Modern CPUs have 4 ALUs, but we use only 3 because random math executes together with other main loop code
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ALU_COUNT = 3,
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};
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enum V4_InstructionList
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{
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MUL, // a*b
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ADD, // a+b + C, C is an unsigned 32-bit constant
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SUB, // a-b
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ROR, // rotate right "a" by "b & 31" bits
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ROL, // rotate left "a" by "b & 31" bits
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XOR, // a^b
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RET, // finish execution
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V4_INSTRUCTION_COUNT = RET,
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};
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// V4_InstructionDefinition is used to generate code from random data
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// Every random sequence of bytes is a valid code
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//
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// There are 8 registers in total:
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// - 4 variable registers
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// - 4 constant registers initialized from loop variables
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//
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// This is why dst_index is 2 bits
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enum V4_InstructionDefinition
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{
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V4_OPCODE_BITS = 3,
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V4_DST_INDEX_BITS = 2,
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V4_SRC_INDEX_BITS = 3,
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};
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struct V4_Instruction
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{
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uint8_t opcode;
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uint8_t dst_index;
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uint8_t src_index;
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uint32_t C;
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};
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#ifndef FORCEINLINE
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#ifdef __GNUC__
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#define FORCEINLINE __attribute__((always_inline)) inline
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#elif _MSC_VER
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#define FORCEINLINE __forceinline
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#else
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#define FORCEINLINE inline
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#endif
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#endif
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#ifndef UNREACHABLE_CODE
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#ifdef __GNUC__
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#define UNREACHABLE_CODE __builtin_unreachable()
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#elif _MSC_VER
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#define UNREACHABLE_CODE __assume(false)
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#else
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#define UNREACHABLE_CODE
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#endif
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#endif
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// Random math interpreter's loop is fully unrolled and inlined to achieve 100% branch prediction on CPU:
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// every switch-case will point to the same destination on every iteration of Cryptonight main loop
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//
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// This is about as fast as it can get without using low-level machine code generation
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static FORCEINLINE void v4_random_math(const struct V4_Instruction* code, v4_reg* r)
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{
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enum
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{
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REG_BITS = sizeof(v4_reg) * 8,
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};
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#define V4_EXEC(i) \
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{ \
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const struct V4_Instruction* op = code + i; \
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const v4_reg src = r[op->src_index]; \
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v4_reg* dst = r + op->dst_index; \
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switch (op->opcode) \
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{ \
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case MUL: \
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*dst *= src; \
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break; \
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case ADD: \
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*dst += src + op->C; \
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break; \
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case SUB: \
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*dst -= src; \
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break; \
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case ROR: \
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{ \
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const uint32_t shift = src % REG_BITS; \
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*dst = (*dst >> shift) | (*dst << ((REG_BITS - shift) % REG_BITS)); \
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} \
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break; \
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case ROL: \
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{ \
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const uint32_t shift = src % REG_BITS; \
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*dst = (*dst << shift) | (*dst >> ((REG_BITS - shift) % REG_BITS)); \
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} \
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break; \
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case XOR: \
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*dst ^= src; \
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break; \
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case RET: \
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return; \
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default: \
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UNREACHABLE_CODE; \
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break; \
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} \
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}
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#define V4_EXEC_10(j) \
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V4_EXEC(j + 0) \
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V4_EXEC(j + 1) \
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V4_EXEC(j + 2) \
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V4_EXEC(j + 3) \
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V4_EXEC(j + 4) \
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V4_EXEC(j + 5) \
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V4_EXEC(j + 6) \
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V4_EXEC(j + 7) \
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V4_EXEC(j + 8) \
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V4_EXEC(j + 9)
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// Generated program can have 60 + a few more (usually 2-3) instructions to achieve required latency
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// I've checked all block heights < 10,000,000 and here is the distribution of program sizes:
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//
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// 60 28495
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// 61 106077
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// 62 2455855
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// 63 5114930
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// 64 1020868
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// 65 1109026
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// 66 151756
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// 67 8429
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// 68 4477
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// 69 87
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// Unroll 70 instructions here
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V4_EXEC_10(0); // instructions 0-9
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V4_EXEC_10(10); // instructions 10-19
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V4_EXEC_10(20); // instructions 20-29
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V4_EXEC_10(30); // instructions 30-39
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V4_EXEC_10(40); // instructions 40-49
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V4_EXEC_10(50); // instructions 50-59
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V4_EXEC_10(60); // instructions 60-69
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#undef V4_EXEC_10
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#undef V4_EXEC
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}
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// If we don't have enough data available, generate more
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static FORCEINLINE void check_data(size_t* data_index, const size_t bytes_needed, int8_t* data, const size_t data_size)
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{
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if (*data_index + bytes_needed > data_size)
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{
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hash_extra_blake(data, data_size, (char*) data);
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*data_index = 0;
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}
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}
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// Generates as many random math operations as possible with given latency and ALU restrictions
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static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_t height)
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{
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// MUL is 3 cycles, 3-way addition and rotations are 2 cycles, SUB/XOR are 1 cycle
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// These latencies match real-life instruction latencies for Intel CPUs starting from Sandy Bridge and up to Skylake/Coffee lake
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//
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// AMD Ryzen has the same latencies except 1-cycle ROR/ROL, so it'll be a bit faster than Intel Sandy Bridge and newer processors
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// Surprisingly, Intel Nehalem also has 1-cycle ROR/ROL, so it'll also be faster than Intel Sandy Bridge and newer processors
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// AMD Bulldozer has 4 cycles latency for MUL (slower than Intel) and 1 cycle for ROR/ROL (faster than Intel), so average performance will be the same
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// Source: https://www.agner.org/optimize/instruction_tables.pdf
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const int op_latency[V4_INSTRUCTION_COUNT] = { 3, 2, 1, 2, 2, 1 };
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// Instruction latencies for theoretical ASIC implementation
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const int asic_op_latency[V4_INSTRUCTION_COUNT] = { 3, 1, 1, 1, 1, 1 };
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// Available ALUs for each instruction
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const int op_ALUs[V4_INSTRUCTION_COUNT] = { ALU_COUNT_MUL, ALU_COUNT, ALU_COUNT, ALU_COUNT, ALU_COUNT, ALU_COUNT };
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int8_t data[32];
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memset(data, 0, sizeof(data));
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uint64_t tmp = SWAP64LE(height);
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memcpy(data, &tmp, sizeof(uint64_t));
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// Set data_index past the last byte in data
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// to trigger full data update with blake hash
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// before we start using it
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size_t data_index = sizeof(data);
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int code_size;
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do {
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int latency[8];
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int asic_latency[8];
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// Tracks previous instruction and value of the source operand for registers R0-R3 throughout code execution
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// byte 0: current value of the destination register
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// byte 1: instruction opcode
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// byte 2: current value of the source register
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//
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// Registers R4-R7 are constant and are treated as having the same value because when we do
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// the same operation twice with two constant source registers, it can be optimized into a single operation
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uint32_t inst_data[8] = { 0, 1, 2, 3, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF };
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bool alu_busy[TOTAL_LATENCY + 1][ALU_COUNT];
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bool is_rotation[V4_INSTRUCTION_COUNT];
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bool rotated[4];
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int rotate_count = 0;
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memset(latency, 0, sizeof(latency));
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memset(asic_latency, 0, sizeof(asic_latency));
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memset(alu_busy, 0, sizeof(alu_busy));
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memset(is_rotation, 0, sizeof(is_rotation));
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memset(rotated, 0, sizeof(rotated));
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is_rotation[ROR] = true;
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is_rotation[ROL] = true;
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int num_retries = 0;
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code_size = 0;
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int total_iterations = 0;
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// Generate random code to achieve minimal required latency for our abstract CPU
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// Try to get this latency for all 4 registers
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while (((latency[0] < TOTAL_LATENCY) || (latency[1] < TOTAL_LATENCY) || (latency[2] < TOTAL_LATENCY) || (latency[3] < TOTAL_LATENCY)) && (num_retries < 64))
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{
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// Fail-safe to guarantee loop termination
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++total_iterations;
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if (total_iterations > 256)
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break;
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check_data(&data_index, 1, data, sizeof(data));
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const uint8_t c = ((uint8_t*)data)[data_index++];
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// MUL = opcodes 0-2
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// ADD = opcode 3
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// SUB = opcode 4
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// ROR/ROL = opcode 5, shift direction is selected randomly
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// XOR = opcodes 6-7
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uint8_t opcode = c & ((1 << V4_OPCODE_BITS) - 1);
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if (opcode == 5)
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{
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check_data(&data_index, 1, data, sizeof(data));
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opcode = (data[data_index++] >= 0) ? ROR : ROL;
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}
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else if (opcode >= 6)
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{
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opcode = XOR;
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}
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else
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{
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opcode = (opcode <= 2) ? MUL : (opcode - 2);
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}
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uint8_t dst_index = (c >> V4_OPCODE_BITS) & ((1 << V4_DST_INDEX_BITS) - 1);
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uint8_t src_index = (c >> (V4_OPCODE_BITS + V4_DST_INDEX_BITS)) & ((1 << V4_SRC_INDEX_BITS) - 1);
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const int a = dst_index;
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int b = src_index;
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// Don't do ADD/SUB/XOR with the same register
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if (((opcode == ADD) || (opcode == SUB) || (opcode == XOR)) && (a == b))
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{
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// a is always < 4, so we don't need to check bounds here
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b = a + 4;
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src_index = b;
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}
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// Don't do rotation with the same destination twice because it's equal to a single rotation
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if (is_rotation[opcode] && rotated[a])
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{
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continue;
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}
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// Don't do the same instruction (except MUL) with the same source value twice because all other cases can be optimized:
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// 2xADD(a, b, C) = ADD(a, b*2, C1+C2), same for SUB and rotations
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// 2xXOR(a, b) = NOP
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if ((opcode != MUL) && ((inst_data[a] & 0xFFFF00) == (opcode << 8) + ((inst_data[b] & 255) << 16)))
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{
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continue;
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}
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// Find which ALU is available (and when) for this instruction
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int next_latency = (latency[a] > latency[b]) ? latency[a] : latency[b];
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int alu_index = -1;
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while (next_latency < TOTAL_LATENCY)
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{
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for (int i = op_ALUs[opcode] - 1; i >= 0; --i)
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{
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if (!alu_busy[next_latency][i])
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{
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// ADD is implemented as two 1-cycle instructions on a real CPU, so do an additional availability check
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if ((opcode == ADD) && alu_busy[next_latency + 1][i])
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{
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continue;
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}
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// Rotation can only start when previous rotation is finished, so do an additional availability check
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if (is_rotation[opcode] && (next_latency < rotate_count * op_latency[opcode]))
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{
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continue;
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}
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alu_index = i;
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break;
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}
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}
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if (alu_index >= 0)
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{
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break;
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}
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++next_latency;
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}
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// Don't generate instructions that leave some register unchanged for more than 7 cycles
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if (next_latency > latency[a] + 7)
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{
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continue;
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}
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next_latency += op_latency[opcode];
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if (next_latency <= TOTAL_LATENCY)
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{
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if (is_rotation[opcode])
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{
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++rotate_count;
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}
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// Mark ALU as busy only for the first cycle when it starts executing the instruction because ALUs are fully pipelined
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alu_busy[next_latency - op_latency[opcode]][alu_index] = true;
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latency[a] = next_latency;
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// ASIC is supposed to have enough ALUs to run as many independent instructions per cycle as possible, so latency calculation for ASIC is simple
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asic_latency[a] = ((asic_latency[a] > asic_latency[b]) ? asic_latency[a] : asic_latency[b]) + asic_op_latency[opcode];
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rotated[a] = is_rotation[opcode];
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inst_data[a] = code_size + (opcode << 8) + ((inst_data[b] & 255) << 16);
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code[code_size].opcode = opcode;
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code[code_size].dst_index = dst_index;
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code[code_size].src_index = src_index;
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code[code_size].C = 0;
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if (opcode == ADD)
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{
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// ADD instruction is implemented as two 1-cycle instructions on a real CPU, so mark ALU as busy for the next cycle too
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alu_busy[next_latency - op_latency[opcode] + 1][alu_index] = true;
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// ADD instruction requires 4 more random bytes for 32-bit constant "C" in "a = a + b + C"
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check_data(&data_index, sizeof(uint32_t), data, sizeof(data));
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uint32_t t;
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memcpy(&t, data + data_index, sizeof(uint32_t));
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code[code_size].C = SWAP32LE(t);
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data_index += sizeof(uint32_t);
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}
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++code_size;
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if (code_size >= NUM_INSTRUCTIONS)
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{
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break;
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}
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}
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else
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{
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++num_retries;
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}
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}
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// ASIC has more execution resources and can extract as much parallelism from the code as possible
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// We need to add a few more MUL and ROR instructions to achieve minimal required latency for ASIC
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// Get this latency for at least 1 of the 4 registers
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const int prev_code_size = code_size;
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while ((asic_latency[0] < TOTAL_LATENCY) && (asic_latency[1] < TOTAL_LATENCY) && (asic_latency[2] < TOTAL_LATENCY) && (asic_latency[3] < TOTAL_LATENCY))
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{
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int min_idx = 0;
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int max_idx = 0;
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for (int i = 1; i < 4; ++i)
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{
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if (asic_latency[i] < asic_latency[min_idx]) min_idx = i;
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if (asic_latency[i] > asic_latency[max_idx]) max_idx = i;
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}
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const uint8_t pattern[3] = { ROR, MUL, MUL };
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const uint8_t opcode = pattern[(code_size - prev_code_size) % 3];
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latency[min_idx] = latency[max_idx] + op_latency[opcode];
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asic_latency[min_idx] = asic_latency[max_idx] + asic_op_latency[opcode];
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code[code_size].opcode = opcode;
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code[code_size].dst_index = min_idx;
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code[code_size].src_index = max_idx;
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code[code_size].C = 0;
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++code_size;
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}
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// There is ~99.8% chance that code_size >= NUM_INSTRUCTIONS here, so second iteration is required rarely
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} while (code_size < NUM_INSTRUCTIONS);
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// Add final instruction to stop the interpreter
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code[code_size].opcode = RET;
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code[code_size].dst_index = 0;
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code[code_size].src_index = 0;
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code[code_size].C = 0;
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return code_size;
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}
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#endif
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