tevador
9af0cbf108
Documentation formatting
5 years ago
tevador
32d827d0a6
Interpreter with bytecode
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Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
5 years ago
tevador
a586751f6b
Removed FPNEG instruction
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Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
5 years ago
tevador
ac4462ad42
Renamed floating point instructions
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Fixed negative source operand for FMUL_M and FDIV_M
5 years ago
tevador
b417fd08ea
16 -> 8 chained programs
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constant address loads are always from L3
5 years ago
tevador
1ee94bef2a
Added ISWAP instruction
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Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
5 years ago
tevador
ab859879a2
loop body = 128 instructions
5 years ago
tevador
20eb549725
Merged load/store of integer and FP registers
5 years ago
tevador
8f2abd6c05
NOP instruction
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register load/store from L3
5 years ago
tevador
005c67f64c
Added explicit STORE instructions
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JIT compiler
5 years ago
tevador
7c049cce8d
Added store instructions
5 years ago
tevador
5b7df0c5e1
Test ASM for a new program structure
5 years ago
tevador
d2cb086221
ASM code generator for "small" programs that fit into the uOP cache
5 years ago
tevador
bd0dba88a8
4 scratchpad segments
5 years ago
tevador
16db607025
Scratchpad size increased to 1 MiB
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New AES-based scratchpad hashing function
5 years ago
tevador
93c324709b
Related to previous changes
5 years ago
tevador
89bc68d093
Memory-bound dataset initialization
5 years ago
tevador
4fb168e249
Large page support for cache
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Bug fixes
5 years ago
tevador
8b1102ee05
Interpreter + async mode
5 years ago
tevador
c2e0122e15
Comparison with CryptoNight
6 years ago
tevador
a7ffe8c19a
Mix dataset cacheline with registers r0-r7
6 years ago
tevador
48d85643de
Dataset intialization algorithm (AES)
6 years ago
tevador
67e741ff22
Reduced x86 code size by 512 bytes (and ecx -> and eax)
6 years ago
tevador
1426fcbab5
Print average program code size
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Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
6 years ago
tevador
2756bcdcfe
Added magic division to JIT compiler
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New B operand selection rules
6 years ago
tevador
451dfc5730
Optimized division by constants
6 years ago
tevador
c02ee4291d
FPROUND - variable flag offset
6 years ago
tevador
e487092f07
Simplified CALL and RET
6 years ago
tevador
557241cd95
JUMP instruction
6 years ago
tevador
6941b2cb69
Reworked instruction set documentation
6 years ago
tevador
d1a808643d
Random accesses - JIT compiler
6 years ago
tevador
b71e0eec65
Optimizations to reduce code size under 32K
6 years ago
tevador
b6d654291f
90 address transformations
6 years ago
tevador
2f6a599ff6
Inlined calls for memory read
6 years ago
tevador
6519fed4d1
Combined prefetch + read into a single step
6 years ago
tevador
4189e4ebc6
Original number of VM instructions
6 years ago
tevador
619bee5418
Random dataset accesses - asm only
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Initial support for large pages
6 years ago
tevador
bf8397b08d
Updated specification
6 years ago
tevador
3caecc7646
Vector FPU instructions
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JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
6 years ago
tevador
a09bee8d60
js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up)
6 years ago
tevador
76b6b05cf2
Unconditional RET
6 years ago
tevador
39c569ae44
Fixed a potential crash in JitCompilerX86
6 years ago
tevador
5bc26348f1
Updated readme with performance data
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Added --help option
6 years ago
tevador
03913d0e81
Run a single thread synchronously
6 years ago
tevador
c05947db09
Bug fixes
6 years ago
tevador
ca59925495
JitCompilerX86: use mmap to allocate an executable buffer
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compile as c++11
6 years ago
tevador
740c40b218
8 branch conditions for CALL/RET
6 years ago
tevador
55afe9646f
Debuggable assembly generator
6 years ago
tevador
fce6e75689
Fixed copyright notice
6 years ago
tevador
ffa67295c4
Instruction statistics
6 years ago