12 Commits (master)

Author	SHA1	Message	Date
tevador	d99af8c51e	Update documentation	5 years ago
tevador	e6ba0a1b7d	Code generator fixups ... - fixed a crash in Instruction::print - new example program - added a design note about the number of x86 instruction per VM instruction	5 years ago
tevador	8a5ead5ce3	Use 'dst' as the CBRANCH condition register ... See issue #43	5 years ago
tevador	03dd2f397f	New sample program	5 years ago
tevador	9e5eac8645	Fixed a chance of CBRANCH looping ... Fixed CBRANCH jump probability being lower than expected	5 years ago
tevador	60d1fa2407	Updated sample program	5 years ago
tevador	3cf6a30076	Fixed biased condition register selection	5 years ago
tevador	ffebc37381	COND_R instruction reworked as CBRANCH ... instruction mod field bits reallocated	5 years ago
tevador	fd7186f873	Changed IADD_RS to use mod.mem	5 years ago
tevador	ff88a57a98	Fixed reading from the red zone	5 years ago
tevador	f66da3911e	Fixed some compilation issues ... Code cleanup	5 years ago
tevador	a8c7137873	Linux makefile ... Exception handling	5 years ago