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@ -40,7 +40,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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namespace randomx {
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static bool isMultiplication(int type) {
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static bool isMultiplication(SuperscalarInstructionType type) {
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return type == SuperscalarInstructionType::IMUL_R || type == SuperscalarInstructionType::IMULH_R || type == SuperscalarInstructionType::ISMULH_R || type == SuperscalarInstructionType::IMUL_RCP;
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}
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@ -167,7 +167,7 @@ namespace randomx {
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const MacroOp& getOp(int index) const {
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return ops_[index];
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}
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int getType() const {
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SuperscalarInstructionType getType() const {
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return type_;
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}
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int getResultOp() const {
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@ -196,7 +196,7 @@ namespace randomx {
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static const SuperscalarInstructionInfo NOP;
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private:
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const char* name_;
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int type_;
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SuperscalarInstructionType type_;
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std::vector<MacroOp> ops_;
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int latency_;
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int resultOp_ = 0;
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@ -204,13 +204,13 @@ namespace randomx {
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int srcOp_;
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SuperscalarInstructionInfo(const char* name)
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: name_(name), type_(-1), latency_(0) {}
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SuperscalarInstructionInfo(const char* name, int type, const MacroOp& op, int srcOp)
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: name_(name), type_(SuperscalarInstructionType::INVALID), latency_(0) {}
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SuperscalarInstructionInfo(const char* name, SuperscalarInstructionType type, const MacroOp& op, int srcOp)
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: name_(name), type_(type), latency_(op.getLatency()), srcOp_(srcOp) {
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ops_.push_back(MacroOp(op));
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}
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template <size_t N>
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SuperscalarInstructionInfo(const char* name, int type, const MacroOp(&arr)[N], int resultOp, int dstOp, int srcOp)
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SuperscalarInstructionInfo(const char* name, SuperscalarInstructionType type, const MacroOp(&arr)[N], int resultOp, int dstOp, int srcOp)
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: name_(name), type_(type), latency_(0), resultOp_(resultOp), dstOp_(dstOp), srcOp_(srcOp) {
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for (unsigned i = 0; i < N; ++i) {
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ops_.push_back(MacroOp(arr[i]));
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@ -267,7 +267,7 @@ namespace randomx {
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const char* getName() const {
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return name_;
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}
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const DecoderBuffer* fetchNext(int instrType, int cycle, int mulCount, Blake2Generator& gen) const {
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const DecoderBuffer* fetchNext(SuperscalarInstructionType instrType, int cycle, int mulCount, Blake2Generator& gen) const {
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//If the current RandomX instruction is "IMULH", the next fetch configuration must be 3-3-10
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//because the full 128-bit multiplication instruction is 3 bytes long and decodes to 2 uOPs on Intel CPUs.
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//Intel CPUs can decode at most 4 uOPs per cycle, so this requires a 2-1-1 configuration for a total of 3 macro ops.
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@ -345,9 +345,9 @@ namespace randomx {
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class RegisterInfo {
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public:
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RegisterInfo() : latency(0), lastOpGroup(-1), lastOpPar(-1), value(0) {}
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RegisterInfo() : latency(0), lastOpGroup(SuperscalarInstructionType::INVALID), lastOpPar(-1), value(0) {}
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int latency;
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int lastOpGroup;
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SuperscalarInstructionType lastOpGroup;
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int lastOpPar;
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int value;
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};
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@ -356,7 +356,7 @@ namespace randomx {
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class SuperscalarInstruction {
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public:
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void toInstr(Instruction& instr) { //translate to a RandomX instruction format
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instr.opcode = getType();
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instr.opcode = (int)getType();
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instr.dst = dst_;
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instr.src = src_ >= 0 ? src_ : dst_;
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instr.setMod(mod_);
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@ -534,7 +534,7 @@ namespace randomx {
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return false;
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}
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int getType() {
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SuperscalarInstructionType getType() {
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return info_->getType();
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}
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int getSource() {
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@ -543,7 +543,7 @@ namespace randomx {
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int getDestination() {
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return dst_;
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}
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int getGroup() {
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SuperscalarInstructionType getGroup() {
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return opGroup_;
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}
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int getGroupPar() {
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@ -562,7 +562,7 @@ namespace randomx {
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int dst_ = -1;
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int mod_;
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uint32_t imm32_;
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int opGroup_;
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SuperscalarInstructionType opGroup_;
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int opGroupPar_;
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bool canReuse_ = false;
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bool groupParIsSource_ = false;
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@ -849,40 +849,40 @@ namespace randomx {
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void executeSuperscalar(int_reg_t(&r)[8], SuperscalarProgram& prog, std::vector<uint64_t> *reciprocals) {
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for (unsigned j = 0; j < prog.getSize(); ++j) {
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Instruction& instr = prog(j);
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switch (instr.opcode)
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switch ((SuperscalarInstructionType)instr.opcode)
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{
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case randomx::SuperscalarInstructionType::ISUB_R:
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case SuperscalarInstructionType::ISUB_R:
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r[instr.dst] -= r[instr.src];
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break;
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case randomx::SuperscalarInstructionType::IXOR_R:
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case SuperscalarInstructionType::IXOR_R:
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r[instr.dst] ^= r[instr.src];
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break;
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case randomx::SuperscalarInstructionType::IADD_RS:
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case SuperscalarInstructionType::IADD_RS:
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r[instr.dst] += r[instr.src] << instr.getModShift();
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break;
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case randomx::SuperscalarInstructionType::IMUL_R:
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case SuperscalarInstructionType::IMUL_R:
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r[instr.dst] *= r[instr.src];
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break;
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case randomx::SuperscalarInstructionType::IROR_C:
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case SuperscalarInstructionType::IROR_C:
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r[instr.dst] = rotr(r[instr.dst], instr.getImm32());
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break;
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case randomx::SuperscalarInstructionType::IADD_C7:
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case randomx::SuperscalarInstructionType::IADD_C8:
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case randomx::SuperscalarInstructionType::IADD_C9:
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case SuperscalarInstructionType::IADD_C7:
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case SuperscalarInstructionType::IADD_C8:
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case SuperscalarInstructionType::IADD_C9:
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r[instr.dst] += signExtend2sCompl(instr.getImm32());
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break;
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case randomx::SuperscalarInstructionType::IXOR_C7:
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case randomx::SuperscalarInstructionType::IXOR_C8:
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case randomx::SuperscalarInstructionType::IXOR_C9:
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case SuperscalarInstructionType::IXOR_C7:
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case SuperscalarInstructionType::IXOR_C8:
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case SuperscalarInstructionType::IXOR_C9:
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r[instr.dst] ^= signExtend2sCompl(instr.getImm32());
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break;
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case randomx::SuperscalarInstructionType::IMULH_R:
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case SuperscalarInstructionType::IMULH_R:
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r[instr.dst] = mulh(r[instr.dst], r[instr.src]);
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break;
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case randomx::SuperscalarInstructionType::ISMULH_R:
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case SuperscalarInstructionType::ISMULH_R:
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r[instr.dst] = smulh(r[instr.dst], r[instr.src]);
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break;
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case randomx::SuperscalarInstructionType::IMUL_RCP:
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case SuperscalarInstructionType::IMUL_RCP:
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if (reciprocals != nullptr)
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r[instr.dst] *= (*reciprocals)[instr.getImm32()];
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else
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