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611 lines
23 KiB
611 lines
23 KiB
/*
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Copyright (c) 2018-2019, tevador <tevador@gmail.com>
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the copyright holder nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <climits>
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#include "assembly_generator_x86.hpp"
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#include "common.hpp"
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#include "reciprocal.h"
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#include "program.hpp"
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#include "superscalar.hpp"
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namespace randomx {
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static const char* regR[] = { "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" };
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static const char* regR32[] = { "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" };
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static const char* regFE[] = { "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regF[] = { "xmm0", "xmm1", "xmm2", "xmm3" };
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static const char* regE[] = { "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regA[] = { "xmm8", "xmm9", "xmm10", "xmm11" };
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static const char* tempRegx = "xmm12";
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static const char* mantissaMaskReg = "xmm13";
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static const char* exponentMaskReg = "xmm14";
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static const char* scaleMaskReg = "xmm15";
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static const char* regIc = "rbx";
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static const char* regIc32 = "ebx";
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static const char* regIc8 = "bl";
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static const char* regScratchpadAddr = "rsi";
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void AssemblyGeneratorX86::generateProgram(Program& prog) {
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for (unsigned i = 0; i < RegistersCount; ++i) {
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registerUsage[i] = -1;
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}
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asmCode.str(std::string()); //clear
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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asmCode << "randomx_isn_" << i << ":" << std::endl;
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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}
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}
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void AssemblyGeneratorX86::generateAsm(SuperscalarProgram& prog) {
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asmCode.str(std::string()); //clear
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#ifdef RANDOMX_ALIGN
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asmCode << "ALIGN 16" << std::endl;
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#endif
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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Instruction& instr = prog(i);
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switch ((SuperscalarInstructionType)instr.opcode)
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{
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case SuperscalarInstructionType::ISUB_R:
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asmCode << "sub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_R:
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asmCode << "xor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case SuperscalarInstructionType::IADD_RS:
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asmCode << "lea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << "]" << std::endl;
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break;
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case SuperscalarInstructionType::IMUL_R:
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asmCode << "imul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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break;
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case SuperscalarInstructionType::IROR_C:
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asmCode << "ror " << regR[instr.dst] << ", " << instr.getImm32() << std::endl;
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break;
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case SuperscalarInstructionType::IADD_C7:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_C7:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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break;
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case SuperscalarInstructionType::IADD_C8:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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#ifdef RANDOMX_ALIGN
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asmCode << "nop" << std::endl;
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#endif
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break;
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case SuperscalarInstructionType::IXOR_C8:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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#ifdef RANDOMX_ALIGN
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asmCode << "nop" << std::endl;
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#endif
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break;
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case SuperscalarInstructionType::IADD_C9:
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asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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#ifdef RANDOMX_ALIGN
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asmCode << "xchg ax, ax ;nop" << std::endl;
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#endif
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break;
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case SuperscalarInstructionType::IXOR_C9:
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asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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#ifdef RANDOMX_ALIGN
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asmCode << "xchg ax, ax ;nop" << std::endl;
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#endif
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break;
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case SuperscalarInstructionType::IMULH_R:
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asmCode << "mov rax, " << regR[instr.dst] << std::endl;
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asmCode << "mul " << regR[instr.src] << std::endl;
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asmCode << "mov " << regR[instr.dst] << ", rdx" << std::endl;
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break;
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case SuperscalarInstructionType::ISMULH_R:
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asmCode << "mov rax, " << regR[instr.dst] << std::endl;
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asmCode << "imul " << regR[instr.src] << std::endl;
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asmCode << "mov " << regR[instr.dst] << ", rdx" << std::endl;
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break;
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case SuperscalarInstructionType::IMUL_RCP:
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asmCode << "mov rax, " << (int64_t)randomx_reciprocal(instr.getImm32()) << std::endl;
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asmCode << "imul " << regR[instr.dst] << ", rax" << std::endl;
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break;
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default:
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UNREACHABLE;
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}
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}
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}
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void AssemblyGeneratorX86::generateC(SuperscalarProgram& prog) {
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asmCode.str(std::string()); //clear
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asmCode << "#include <stdint.h>" << std::endl;
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asmCode << "#if defined(__SIZEOF_INT128__)" << std::endl;
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asmCode << " static inline uint64_t mulh(uint64_t a, uint64_t b) {" << std::endl;
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asmCode << " return ((unsigned __int128)a * b) >> 64;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " static inline int64_t smulh(int64_t a, int64_t b) {" << std::endl;
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asmCode << " return ((__int128)a * b) >> 64;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_MULH" << std::endl;
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asmCode << " #define HAVE_SMULH" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#if defined(_MSC_VER)" << std::endl;
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asmCode << " #define HAS_VALUE(X) X ## 0" << std::endl;
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asmCode << " #define EVAL_DEFINE(X) HAS_VALUE(X)" << std::endl;
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asmCode << " #include <intrin.h>" << std::endl;
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asmCode << " #include <stdlib.h>" << std::endl;
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asmCode << " static __inline uint64_t rotr(uint64_t x , int c) {" << std::endl;
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asmCode << " return _rotr64(x, c);" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_ROTR" << std::endl;
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asmCode << " #if EVAL_DEFINE(__MACHINEARM64_X64(1))" << std::endl;
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asmCode << " static __inline uint64_t mulh(uint64_t a, uint64_t b) {" << std::endl;
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asmCode << " return __umulh(a, b);" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_MULH" << std::endl;
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asmCode << " #endif" << std::endl;
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asmCode << " #if EVAL_DEFINE(__MACHINEX64(1))" << std::endl;
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asmCode << " static __inline int64_t smulh(int64_t a, int64_t b) {" << std::endl;
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asmCode << " int64_t hi;" << std::endl;
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asmCode << " _mul128(a, b, &hi);" << std::endl;
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asmCode << " return hi;" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_SMULH" << std::endl;
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asmCode << " #endif" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#ifndef HAVE_ROTR" << std::endl;
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asmCode << " static inline uint64_t rotr(uint64_t a, int b) {" << std::endl;
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asmCode << " return (a >> b) | (a << (64 - b));" << std::endl;
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asmCode << " }" << std::endl;
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asmCode << " #define HAVE_ROTR" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "#if !defined(HAVE_MULH) || !defined(HAVE_SMULH) || !defined(HAVE_ROTR)" << std::endl;
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asmCode << " #error \"Required functions are not defined\"" << std::endl;
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asmCode << "#endif" << std::endl;
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asmCode << "void superScalar(uint64_t r[8]) {" << std::endl;
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asmCode << "uint64_t r8 = r[0], r9 = r[1], r10 = r[2], r11 = r[3], r12 = r[4], r13 = r[5], r14 = r[6], r15 = r[7];" << std::endl;
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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Instruction& instr = prog(i);
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switch ((SuperscalarInstructionType)instr.opcode)
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{
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case SuperscalarInstructionType::ISUB_R:
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asmCode << regR[instr.dst] << " -= " << regR[instr.src] << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_R:
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asmCode << regR[instr.dst] << " ^= " << regR[instr.src] << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IADD_RS:
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asmCode << regR[instr.dst] << " += " << regR[instr.src] << "*" << (1 << (instr.getModShift())) << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IMUL_R:
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asmCode << regR[instr.dst] << " *= " << regR[instr.src] << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IROR_C:
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asmCode << regR[instr.dst] << " = rotr(" << regR[instr.dst] << ", " << instr.getImm32() << ");" << std::endl;
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break;
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case SuperscalarInstructionType::IADD_C7:
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case SuperscalarInstructionType::IADD_C8:
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case SuperscalarInstructionType::IADD_C9:
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asmCode << regR[instr.dst] << " += " << (int32_t)instr.getImm32() << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IXOR_C7:
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case SuperscalarInstructionType::IXOR_C8:
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case SuperscalarInstructionType::IXOR_C9:
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asmCode << regR[instr.dst] << " ^= " << (int32_t)instr.getImm32() << ";" << std::endl;
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break;
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case SuperscalarInstructionType::IMULH_R:
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asmCode << regR[instr.dst] << " = mulh(" << regR[instr.dst] << ", " << regR[instr.src] << ");" << std::endl;
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break;
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case SuperscalarInstructionType::ISMULH_R:
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asmCode << regR[instr.dst] << " = smulh(" << regR[instr.dst] << ", " << regR[instr.src] << ");" << std::endl;
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break;
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case SuperscalarInstructionType::IMUL_RCP:
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asmCode << regR[instr.dst] << " *= " << (int64_t)randomx_reciprocal(instr.getImm32()) << ";" << std::endl;
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break;
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default:
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UNREACHABLE;
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}
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}
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asmCode << "r[0] = r8; r[1] = r9; r[2] = r10; r[3] = r11; r[4] = r12; r[5] = r13; r[6] = r14; r[7] = r15;" << std::endl;
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asmCode << "}" << std::endl;
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}
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void AssemblyGeneratorX86::traceint(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush " << regR[instr.dst] << std::endl;
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}
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}
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void AssemblyGeneratorX86::traceflt(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush 0" << std::endl;
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}
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}
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void AssemblyGeneratorX86::tracenop(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush 0" << std::endl;
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}
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}
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void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) {
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asmCode << "\t; " << instr;
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auto generator = engine[instr.opcode];
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(this->*generator)(instr, i);
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}
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void AssemblyGeneratorX86::genAddressReg(Instruction& instr, const char* reg = "eax") {
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asmCode << "\tlea " << reg << ", [" << regR32[instr.src] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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asmCode << "\tand " << reg << ", " << ((instr.getModMem()) ? ScratchpadL1Mask : ScratchpadL2Mask) << std::endl;
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}
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void AssemblyGeneratorX86::genAddressRegDst(Instruction& instr, int maskAlign = 8) {
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asmCode << "\tlea eax, [" << regR32[instr.dst] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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int mask;
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if (instr.getModCond() < StoreL3Condition) {
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mask = instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask;
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}
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else {
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mask = ScratchpadL3Mask;
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}
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asmCode << "\tand eax" << ", " << (mask & (-maskAlign)) << std::endl;
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}
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int32_t AssemblyGeneratorX86::genAddressImm(Instruction& instr) {
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return (int32_t)instr.getImm32() & ScratchpadL3Mask;
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}
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void AssemblyGeneratorX86::h_IADD_RS(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if(instr.dst == RegisterNeedsDisplacement)
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
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else
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << "]" << std::endl;
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traceint(instr);
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}
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void AssemblyGeneratorX86::h_IADD_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
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}
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else {
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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void AssemblyGeneratorX86::h_ISUB_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\tsub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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}
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traceint(instr);
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}
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void AssemblyGeneratorX86::h_ISUB_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
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}
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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void AssemblyGeneratorX86::h_IMUL_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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asmCode << "\timul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\timul " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
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}
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traceint(instr);
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}
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void AssemblyGeneratorX86::h_IMUL_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
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}
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else {
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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void AssemblyGeneratorX86::h_IMULH_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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void AssemblyGeneratorX86::h_IMULH_M(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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if (instr.src != instr.dst) {
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genAddressReg(instr, "ecx");
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul qword ptr [" << regScratchpadAddr << "+rcx]" << std::endl;
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}
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else {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
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}
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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void AssemblyGeneratorX86::h_ISMULH_R(Instruction& instr, int i) {
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registerUsage[instr.dst] = i;
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
|
asmCode << "\timul " << regR[instr.src] << std::endl;
|
|
asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_ISMULH_M(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
genAddressReg(instr, "ecx");
|
|
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
|
asmCode << "\timul qword ptr [" << regScratchpadAddr << "+rcx]" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
|
|
asmCode << "\timul qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
|
|
}
|
|
asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_INEG_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
asmCode << "\tneg " << regR[instr.dst] << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_IXOR_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
asmCode << "\txor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\txor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl;
|
|
}
|
|
traceint(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_IXOR_M(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
genAddressReg(instr);
|
|
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
|
|
}
|
|
traceint(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_IROR_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
|
|
asmCode << "\tror " << regR[instr.dst] << ", cl" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\tror " << regR[instr.dst] << ", " << (instr.getImm32() & 63) << std::endl;
|
|
}
|
|
traceint(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_IROL_R(Instruction& instr, int i) {
|
|
registerUsage[instr.dst] = i;
|
|
if (instr.src != instr.dst) {
|
|
asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
|
|
asmCode << "\trol " << regR[instr.dst] << ", cl" << std::endl;
|
|
}
|
|
else {
|
|
asmCode << "\trol " << regR[instr.dst] << ", " << (instr.getImm32() & 63) << std::endl;
|
|
}
|
|
traceint(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_IMUL_RCP(Instruction& instr, int i) {
|
|
uint64_t divisor = instr.getImm32();
|
|
if (!isZeroOrPowerOf2(divisor)) {
|
|
registerUsage[instr.dst] = i;
|
|
asmCode << "\tmov rax, " << randomx_reciprocal(divisor) << std::endl;
|
|
asmCode << "\timul " << regR[instr.dst] << ", rax" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
else {
|
|
tracenop(instr);
|
|
}
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_ISWAP_R(Instruction& instr, int i) {
|
|
if (instr.src != instr.dst) {
|
|
registerUsage[instr.dst] = i;
|
|
registerUsage[instr.src] = i;
|
|
asmCode << "\txchg " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
|
|
traceint(instr);
|
|
}
|
|
else {
|
|
tracenop(instr);
|
|
}
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FSWAP_R(Instruction& instr, int i) {
|
|
asmCode << "\tshufpd " << regFE[instr.dst] << ", " << regFE[instr.dst] << ", 1" << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FADD_R(Instruction& instr, int i) {
|
|
instr.dst %= RegisterCountFlt;
|
|
instr.src %= RegisterCountFlt;
|
|
asmCode << "\taddpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FADD_M(Instruction& instr, int i) {
|
|
instr.dst %= RegisterCountFlt;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
|
|
asmCode << "\taddpd " << regF[instr.dst] << ", " << tempRegx << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FSUB_R(Instruction& instr, int i) {
|
|
instr.dst %= RegisterCountFlt;
|
|
instr.src %= RegisterCountFlt;
|
|
asmCode << "\tsubpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FSUB_M(Instruction& instr, int i) {
|
|
instr.dst %= RegisterCountFlt;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
|
|
asmCode << "\tsubpd " << regF[instr.dst] << ", " << tempRegx << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FSCAL_R(Instruction& instr, int i) {
|
|
instr.dst %= RegisterCountFlt;
|
|
asmCode << "\txorps " << regF[instr.dst] << ", " << scaleMaskReg << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FMUL_R(Instruction& instr, int i) {
|
|
instr.dst %= RegisterCountFlt;
|
|
instr.src %= RegisterCountFlt;
|
|
asmCode << "\tmulpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FDIV_M(Instruction& instr, int i) {
|
|
instr.dst %= RegisterCountFlt;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
|
|
asmCode << "\tandps " << tempRegx << ", " << mantissaMaskReg << std::endl;
|
|
asmCode << "\torps " << tempRegx << ", " << exponentMaskReg << std::endl;
|
|
asmCode << "\tdivpd " << regE[instr.dst] << ", " << tempRegx << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_FSQRT_R(Instruction& instr, int i) {
|
|
instr.dst %= RegisterCountFlt;
|
|
asmCode << "\tsqrtpd " << regE[instr.dst] << ", " << regE[instr.dst] << std::endl;
|
|
traceflt(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_CFROUND(Instruction& instr, int i) {
|
|
asmCode << "\tmov rax, " << regR[instr.src] << std::endl;
|
|
int rotate = (13 - (instr.getImm32() & 63)) & 63;
|
|
if (rotate != 0)
|
|
asmCode << "\trol rax, " << rotate << std::endl;
|
|
asmCode << "\tand eax, 24576" << std::endl;
|
|
asmCode << "\tor eax, 40896" << std::endl;
|
|
asmCode << "\tpush rax" << std::endl;
|
|
asmCode << "\tldmxcsr dword ptr [rsp]" << std::endl;
|
|
asmCode << "\tpop rax" << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_CBRANCH(Instruction& instr, int i) {
|
|
int reg = instr.dst;
|
|
int target = registerUsage[reg] + 1;
|
|
int shift = instr.getModCond() + ConditionOffset;
|
|
int32_t imm = instr.getImm32() | (1L << shift);
|
|
if (ConditionOffset > 0 || shift > 0)
|
|
imm &= ~(1L << (shift - 1));
|
|
asmCode << "\tadd " << regR[reg] << ", " << imm << std::endl;
|
|
asmCode << "\ttest " << regR[reg] << ", " << (ConditionMask << shift) << std::endl;
|
|
asmCode << "\tjz randomx_isn_" << target << std::endl;
|
|
//mark all registers as used
|
|
for (unsigned j = 0; j < RegistersCount; ++j) {
|
|
registerUsage[j] = i;
|
|
}
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_ISTORE(Instruction& instr, int i) {
|
|
genAddressRegDst(instr);
|
|
asmCode << "\tmov qword ptr [" << regScratchpadAddr << "+rax], " << regR[instr.src] << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_NOP(Instruction& instr, int i) {
|
|
asmCode << "\tnop" << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
#include "instruction_weights.hpp"
|
|
#define INST_HANDLE(x) REPN(&AssemblyGeneratorX86::h_##x, WT(x))
|
|
|
|
InstructionGenerator AssemblyGeneratorX86::engine[256] = {
|
|
INST_HANDLE(IADD_RS)
|
|
INST_HANDLE(IADD_M)
|
|
INST_HANDLE(ISUB_R)
|
|
INST_HANDLE(ISUB_M)
|
|
INST_HANDLE(IMUL_R)
|
|
INST_HANDLE(IMUL_M)
|
|
INST_HANDLE(IMULH_R)
|
|
INST_HANDLE(IMULH_M)
|
|
INST_HANDLE(ISMULH_R)
|
|
INST_HANDLE(ISMULH_M)
|
|
INST_HANDLE(IMUL_RCP)
|
|
INST_HANDLE(INEG_R)
|
|
INST_HANDLE(IXOR_R)
|
|
INST_HANDLE(IXOR_M)
|
|
INST_HANDLE(IROR_R)
|
|
INST_HANDLE(IROL_R)
|
|
INST_HANDLE(ISWAP_R)
|
|
INST_HANDLE(FSWAP_R)
|
|
INST_HANDLE(FADD_R)
|
|
INST_HANDLE(FADD_M)
|
|
INST_HANDLE(FSUB_R)
|
|
INST_HANDLE(FSUB_M)
|
|
INST_HANDLE(FSCAL_R)
|
|
INST_HANDLE(FMUL_R)
|
|
INST_HANDLE(FDIV_M)
|
|
INST_HANDLE(FSQRT_R)
|
|
INST_HANDLE(CBRANCH)
|
|
INST_HANDLE(CFROUND)
|
|
INST_HANDLE(ISTORE)
|
|
INST_HANDLE(NOP)
|
|
};
|
|
} |