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@ -725,6 +725,7 @@ The reference CPU is loosely based on the [Intel Ivy Bridge microarchitecture](h
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* The CPU can decode at most 16 bytes of code per cycle and at most 4 Micro-ops per cycle.
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*Table 6.2.1 - Macro-ops*
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|Macro-op|latency|size|1st Micro-op|2nd Micro-op|
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|-|-|-|-|-|
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|`sub_rr`|1|3|P015|-|
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