Decrease the frequency of FADD/FSUB in favor of FMUL (#77)
* this better matches CPU capabilities since execution ports are usually split 1:1 between fadd and fmul * the frequency of FSWAP_R decreased from 8 to 4 (it's ASIC-friendly) * activate IROL_R instruction1.1.6-wow
parent
83498cddf2
commit
91cd35ff13
Loading…
Reference in new issue