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@ -17,10 +17,6 @@ You should have received a copy of the GNU General Public License
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along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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//#define TRACE
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//#define FPUCHECK
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#define RANDOMX_JUMP
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#include <iostream>
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#include <iomanip>
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#include <stdexcept>
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@ -33,12 +29,6 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#include "intrin_portable.h"
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#include "reciprocal.h"
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#ifdef FPUCHECK
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constexpr bool fpuCheck = true;
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#else
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constexpr bool fpuCheck = false;
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#endif
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namespace randomx {
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static int_reg_t Zero = 0;
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@ -53,49 +43,16 @@ namespace randomx {
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void InterpretedVm<Allocator, softAes>::run(void* seed) {
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VmBase<Allocator, softAes>::generateProgram(seed);
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randomx_vm::initialize();
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for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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program(i).src %= RegistersCount;
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program(i).dst %= RegistersCount;
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}
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execute();
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::executeBytecode(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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for (int ic = 0; ic < RANDOMX_PROGRAM_SIZE; ++ic) {
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executeBytecode(ic, r, f, e, a);
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void InterpretedVm<Allocator, softAes>::executeBytecode(int_reg_t(&r)[RegistersCount], __m128d (&f)[RegisterCountFlt], __m128d (&e)[RegisterCountFlt], __m128d (&a)[RegisterCountFlt]) {
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for (int pc = 0; pc < RANDOMX_PROGRAM_SIZE; ++pc) {
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executeBytecode(pc, r, f, e, a);
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}
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}
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static void print(int_reg_t r) {
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std::cout << std::hex << std::setw(16) << std::setfill('0') << r << std::endl;
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}
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static void print(__m128d f) {
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uint64_t lo = *(((uint64_t*)&f) + 0);
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uint64_t hi = *(((uint64_t*)&f) + 1);
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std::cout << std::hex << std::setw(16) << std::setfill('0') << hi << '-' << std::hex << std::setw(16) << std::setfill('0') << lo << std::endl;
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}
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static void printState(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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for (int i = 0; i < 8; ++i) {
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std::cout << "r" << i << " = "; print(r[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "f" << i << " = "; print(f[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "e" << i << " = "; print(e[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "a" << i << " = "; print(a[i]);
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}
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}
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static bool isDenormal(double x) {
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return std::fpclassify(x) == FP_SUBNORMAL;
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}
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template<class Allocator, bool softAes>
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FORCE_INLINE void* InterpretedVm<Allocator, softAes>::getScratchpadAddress(InstructionByteCode& ibc) {
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uint32_t addr = (*ibc.isrc + ibc.imm) & ibc.memMask;
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@ -113,9 +70,8 @@ namespace randomx {
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::executeBytecode(int& ic, int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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auto& ibc = byteCode[ic];
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if (trace && ibc.type != InstructionType::NOP) std::cout << std::dec << std::setw(3) << ic << " " << program(ic);
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void InterpretedVm<Allocator, softAes>::executeBytecode(int& pc, int_reg_t(&r)[RegistersCount], __m128d (&f)[RegisterCountFlt], __m128d (&e)[RegisterCountFlt], __m128d (&a)[RegisterCountFlt]) {
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auto& ibc = byteCode[pc];
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switch (ibc.type)
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{
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case InstructionType::IADD_RS: {
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@ -225,11 +181,11 @@ namespace randomx {
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} break;
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case InstructionType::COND_R: {
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#ifdef RANDOMX_JUMP
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#if RANDOMX_JUMP
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*ibc.creg += (1 << ibc.shift);
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const uint64_t conditionMask = ((1ULL << RANDOMX_CONDITION_BITS) - 1) << ibc.shift;
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const uint64_t conditionMask = ((1ULL << RANDOMX_JUMP_BITS) - 1) << ibc.shift;
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if ((*ibc.creg & conditionMask) == 0) {
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ic = ibc.target;
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pc = ibc.target;
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break;
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}
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#endif
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@ -251,50 +207,23 @@ namespace randomx {
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default:
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UNREACHABLE;
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}
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if (trace && ibc.type != InstructionType::NOP) {
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if(ibc.type < 20 || ibc.type == 31 || ibc.type == 32)
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print(*ibc.idst);
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else //if(ibc.type >= 20 && ibc.type <= 30)
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print(0);
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}
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#ifdef FPUCHECK
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if (ibc.type >= 26 && ibc.type <= 30) {
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double lo = *(((double*)ibc.fdst) + 0);
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double hi = *(((double*)ibc.fdst) + 1);
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if (lo <= 0 || hi <= 0) {
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std::stringstream ss;
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ss << "Underflow in operation " << ibc.type;
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printState(r, f, e, a);
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throw std::runtime_error(ss.str());
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}
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}
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#endif
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::execute() {
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int_reg_t r[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
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__m128d f[4];
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__m128d e[4];
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__m128d a[4];
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int_reg_t r[RegistersCount] = { 0 };
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__m128d f[RegisterCountFlt];
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__m128d e[RegisterCountFlt];
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__m128d a[RegisterCountFlt];
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a[0] = _mm_load_pd(®.a[0].lo);
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a[1] = _mm_load_pd(®.a[1].lo);
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a[2] = _mm_load_pd(®.a[2].lo);
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a[3] = _mm_load_pd(®.a[3].lo);
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for(unsigned i = 0; i < RegisterCountFlt; ++i)
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a[i] = _mm_load_pd(®.a[i].lo);
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precompileProgram(r, f, e, a);
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uint32_t spAddr0 = mem.mx;
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uint32_t spAddr1 = mem.ma;
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if (trace) {
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std::cout << "execute (reg: r" << config.readReg0 << ", r" << config.readReg1 << ", r" << config.readReg2 << ", r" << config.readReg3 << ")" << std::endl;
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std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
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std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
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printState(r, f, e, a);
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}
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for(unsigned ic = 0; ic < RANDOMX_PROGRAM_ITERATIONS; ++ic) {
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uint64_t spMix = r[config.readReg0] ^ r[config.readReg1];
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spAddr0 ^= spMix;
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@ -302,31 +231,14 @@ namespace randomx {
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spAddr1 ^= spMix >> 32;
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spAddr1 &= ScratchpadL3Mask64;
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r[0] ^= load64(scratchpad + spAddr0 + 0);
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r[1] ^= load64(scratchpad + spAddr0 + 8);
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r[2] ^= load64(scratchpad + spAddr0 + 16);
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r[3] ^= load64(scratchpad + spAddr0 + 24);
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r[4] ^= load64(scratchpad + spAddr0 + 32);
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r[5] ^= load64(scratchpad + spAddr0 + 40);
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r[6] ^= load64(scratchpad + spAddr0 + 48);
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r[7] ^= load64(scratchpad + spAddr0 + 56);
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f[0] = load_cvt_i32x2(scratchpad + spAddr1 + 0);
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f[1] = load_cvt_i32x2(scratchpad + spAddr1 + 8);
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f[2] = load_cvt_i32x2(scratchpad + spAddr1 + 16);
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f[3] = load_cvt_i32x2(scratchpad + spAddr1 + 24);
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e[0] = maskRegisterExponentMantissa(load_cvt_i32x2(scratchpad + spAddr1 + 32));
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e[1] = maskRegisterExponentMantissa(load_cvt_i32x2(scratchpad + spAddr1 + 40));
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e[2] = maskRegisterExponentMantissa(load_cvt_i32x2(scratchpad + spAddr1 + 48));
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e[3] = maskRegisterExponentMantissa(load_cvt_i32x2(scratchpad + spAddr1 + 56));
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if (trace) {
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std::cout << "iteration " << std::dec << ic << std::endl;
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std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
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std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
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printState(r, f, e, a);
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std::cout << "-----------------------------------" << std::endl;
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}
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for (unsigned i = 0; i < RegistersCount; ++i)
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r[i] ^= load64(scratchpad + spAddr0 + 8 * i);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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f[i] = load_cvt_i32x2(scratchpad + spAddr1 + 8 * i);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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e[i] = maskRegisterExponentMantissa(load_cvt_i32x2(scratchpad + spAddr1 + 8 * (RegisterCountFlt + i)));
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executeBytecode(r, f, e, a);
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@ -335,72 +247,33 @@ namespace randomx {
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datasetRead(datasetOffset + mem.ma, r);
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std::swap(mem.mx, mem.ma);
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if (trace) {
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std::cout << "iteration " << std::dec << ic << std::endl;
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std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
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std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
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printState(r, f, e, a);
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std::cout << "===================================" << std::endl;
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}
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for (unsigned i = 0; i < RegistersCount; ++i)
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store64(scratchpad + spAddr1 + 8 * i, r[i]);
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store64(scratchpad + spAddr1 + 0, r[0]);
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store64(scratchpad + spAddr1 + 8, r[1]);
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store64(scratchpad + spAddr1 + 16, r[2]);
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store64(scratchpad + spAddr1 + 24, r[3]);
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store64(scratchpad + spAddr1 + 32, r[4]);
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store64(scratchpad + spAddr1 + 40, r[5]);
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store64(scratchpad + spAddr1 + 48, r[6]);
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store64(scratchpad + spAddr1 + 56, r[7]);
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f[0] = _mm_xor_pd(f[0], e[0]);
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f[1] = _mm_xor_pd(f[1], e[1]);
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f[2] = _mm_xor_pd(f[2], e[2]);
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f[3] = _mm_xor_pd(f[3], e[3]);
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#ifdef FPUCHECK
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for(int i = 0; i < 4; ++i) {
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double lo = *(((double*)&f[i]) + 0);
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double hi = *(((double*)&f[i]) + 1);
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if (isDenormal(lo) || isDenormal(hi)) {
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std::stringstream ss;
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ss << "Denormal f" << i;
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throw std::runtime_error(ss.str());
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}
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}
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#endif
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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f[i] = _mm_xor_pd(f[i], e[i]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 0), f[0]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 16), f[1]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 32), f[2]);
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_mm_store_pd((double*)(scratchpad + spAddr0 + 48), f[3]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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_mm_store_pd((double*)(scratchpad + spAddr0 + 16 * i), f[i]);
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spAddr0 = 0;
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spAddr1 = 0;
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}
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store64(®.r[0], r[0]);
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store64(®.r[1], r[1]);
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store64(®.r[2], r[2]);
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store64(®.r[3], r[3]);
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store64(®.r[4], r[4]);
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store64(®.r[5], r[5]);
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store64(®.r[6], r[6]);
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store64(®.r[7], r[7]);
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_mm_store_pd(®.f[0].lo, f[0]);
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_mm_store_pd(®.f[1].lo, f[1]);
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_mm_store_pd(®.f[2].lo, f[2]);
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_mm_store_pd(®.f[3].lo, f[3]);
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|
|
_mm_store_pd(®.e[0].lo, e[0]);
|
|
|
|
|
_mm_store_pd(®.e[1].lo, e[1]);
|
|
|
|
|
_mm_store_pd(®.e[2].lo, e[2]);
|
|
|
|
|
_mm_store_pd(®.e[3].lo, e[3]);
|
|
|
|
|
for (unsigned i = 0; i < RegistersCount; ++i)
|
|
|
|
|
store64(®.r[i], r[i]);
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < RegisterCountFlt; ++i)
|
|
|
|
|
_mm_store_pd(®.f[i].lo, f[i]);
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < RegisterCountFlt; ++i)
|
|
|
|
|
_mm_store_pd(®.e[i].lo, e[i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int getConditionRegister(int(®isterUsage)[8]) {
|
|
|
|
|
static int getConditionRegister(int(®isterUsage)[RegistersCount]) {
|
|
|
|
|
int min = INT_MAX;
|
|
|
|
|
int minIndex;
|
|
|
|
|
for (unsigned i = 0; i < 8; ++i) {
|
|
|
|
|
for (unsigned i = 0; i < RegistersCount; ++i) {
|
|
|
|
|
if (registerUsage[i] < min) {
|
|
|
|
|
min = registerUsage[i];
|
|
|
|
|
minIndex = i;
|
|
|
|
|
@ -410,7 +283,7 @@ namespace randomx {
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template<class Allocator, bool softAes>
|
|
|
|
|
void InterpretedVm<Allocator, softAes>::datasetRead(uint32_t address, int_reg_t(&r)[8]) {
|
|
|
|
|
void InterpretedVm<Allocator, softAes>::datasetRead(uint32_t address, int_reg_t(&r)[RegistersCount]) {
|
|
|
|
|
uint64_t* datasetLine = (uint64_t*)(mem.memory + address);
|
|
|
|
|
for (int i = 0; i < RegistersCount; ++i)
|
|
|
|
|
r[i] ^= datasetLine[i];
|
|
|
|
|
@ -419,9 +292,9 @@ namespace randomx {
|
|
|
|
|
#include "instruction_weights.hpp"
|
|
|
|
|
|
|
|
|
|
template<class Allocator, bool softAes>
|
|
|
|
|
void InterpretedVm<Allocator, softAes>::precompileProgram(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
|
|
|
|
|
int registerUsage[8];
|
|
|
|
|
for (unsigned i = 0; i < 8; ++i) {
|
|
|
|
|
void InterpretedVm<Allocator, softAes>::precompileProgram(int_reg_t(&r)[RegistersCount], __m128d (&f)[RegisterCountFlt], __m128d (&e)[RegisterCountFlt], __m128d (&a)[RegisterCountFlt]) {
|
|
|
|
|
int registerUsage[RegistersCount];
|
|
|
|
|
for (unsigned i = 0; i < RegistersCount; ++i) {
|
|
|
|
|
registerUsage[i] = -1;
|
|
|
|
|
}
|
|
|
|
|
for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
|
|
|
|
|
@ -443,7 +316,7 @@ namespace randomx {
|
|
|
|
|
ibc.shift = instr.getModMem();
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IADD_M) {
|
|
|
|
|
@ -452,7 +325,7 @@ namespace randomx {
|
|
|
|
|
ibc.type = InstructionType::IADD_M;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
if (instr.src != instr.dst) {
|
|
|
|
|
if (src != dst) {
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
|
|
|
}
|
|
|
|
|
@ -460,7 +333,7 @@ namespace randomx {
|
|
|
|
|
ibc.isrc = &Zero;
|
|
|
|
|
ibc.memMask = ScratchpadL3Mask;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(ISUB_R) {
|
|
|
|
|
@ -475,7 +348,7 @@ namespace randomx {
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
ibc.isrc = &ibc.imm;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(ISUB_M) {
|
|
|
|
|
@ -484,7 +357,7 @@ namespace randomx {
|
|
|
|
|
ibc.type = InstructionType::ISUB_M;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
if (instr.src != instr.dst) {
|
|
|
|
|
if (src != dst) {
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
|
|
|
}
|
|
|
|
|
@ -492,7 +365,7 @@ namespace randomx {
|
|
|
|
|
ibc.isrc = &Zero;
|
|
|
|
|
ibc.memMask = ScratchpadL3Mask;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IMUL_R) {
|
|
|
|
|
@ -507,7 +380,7 @@ namespace randomx {
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
ibc.isrc = &ibc.imm;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IMUL_M) {
|
|
|
|
|
@ -516,7 +389,7 @@ namespace randomx {
|
|
|
|
|
ibc.type = InstructionType::IMUL_M;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
if (instr.src != instr.dst) {
|
|
|
|
|
if (src != dst) {
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
|
|
|
}
|
|
|
|
|
@ -524,7 +397,7 @@ namespace randomx {
|
|
|
|
|
ibc.isrc = &Zero;
|
|
|
|
|
ibc.memMask = ScratchpadL3Mask;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IMULH_R) {
|
|
|
|
|
@ -533,7 +406,7 @@ namespace randomx {
|
|
|
|
|
ibc.type = InstructionType::IMULH_R;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IMULH_M) {
|
|
|
|
|
@ -542,7 +415,7 @@ namespace randomx {
|
|
|
|
|
ibc.type = InstructionType::IMULH_M;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
if (instr.src != instr.dst) {
|
|
|
|
|
if (src != dst) {
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
|
|
|
}
|
|
|
|
|
@ -550,7 +423,7 @@ namespace randomx {
|
|
|
|
|
ibc.isrc = &Zero;
|
|
|
|
|
ibc.memMask = ScratchpadL3Mask;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(ISMULH_R) {
|
|
|
|
|
@ -559,7 +432,7 @@ namespace randomx {
|
|
|
|
|
ibc.type = InstructionType::ISMULH_R;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(ISMULH_M) {
|
|
|
|
|
@ -568,7 +441,7 @@ namespace randomx {
|
|
|
|
|
ibc.type = InstructionType::ISMULH_M;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
if (instr.src != instr.dst) {
|
|
|
|
|
if (src != dst) {
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
|
|
|
}
|
|
|
|
|
@ -576,7 +449,7 @@ namespace randomx {
|
|
|
|
|
ibc.isrc = &Zero;
|
|
|
|
|
ibc.memMask = ScratchpadL3Mask;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IMUL_RCP) {
|
|
|
|
|
@ -587,7 +460,7 @@ namespace randomx {
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.imm = randomx_reciprocal(divisor);
|
|
|
|
|
ibc.isrc = &ibc.imm;
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
ibc.type = InstructionType::NOP;
|
|
|
|
|
@ -598,7 +471,7 @@ namespace randomx {
|
|
|
|
|
auto dst = instr.dst % RegistersCount;
|
|
|
|
|
ibc.type = InstructionType::INEG_R;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IXOR_R) {
|
|
|
|
|
@ -613,7 +486,7 @@ namespace randomx {
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
ibc.isrc = &ibc.imm;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IXOR_M) {
|
|
|
|
|
@ -622,7 +495,7 @@ namespace randomx {
|
|
|
|
|
ibc.type = InstructionType::IXOR_M;
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
|
|
|
if (instr.src != instr.dst) {
|
|
|
|
|
if (src != dst) {
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
|
|
|
}
|
|
|
|
|
@ -630,7 +503,7 @@ namespace randomx {
|
|
|
|
|
ibc.isrc = &Zero;
|
|
|
|
|
ibc.memMask = ScratchpadL3Mask;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IROR_R) {
|
|
|
|
|
@ -645,7 +518,7 @@ namespace randomx {
|
|
|
|
|
ibc.imm = instr.getImm32();
|
|
|
|
|
ibc.isrc = &ibc.imm;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(IROL_R) {
|
|
|
|
|
@ -660,7 +533,7 @@ namespace randomx {
|
|
|
|
|
ibc.imm = instr.getImm32();
|
|
|
|
|
ibc.isrc = &ibc.imm;
|
|
|
|
|
}
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(ISWAP_R) {
|
|
|
|
|
@ -670,8 +543,8 @@ namespace randomx {
|
|
|
|
|
ibc.idst = &r[dst];
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
ibc.type = InstructionType::ISWAP_R;
|
|
|
|
|
registerUsage[instr.dst] = i;
|
|
|
|
|
registerUsage[instr.src] = i;
|
|
|
|
|
registerUsage[dst] = i;
|
|
|
|
|
registerUsage[src] = i;
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
ibc.type = InstructionType::NOP;
|
|
|
|
|
@ -681,23 +554,23 @@ namespace randomx {
|
|
|
|
|
CASE_REP(FSWAP_R) {
|
|
|
|
|
auto dst = instr.dst % RegistersCount;
|
|
|
|
|
ibc.type = InstructionType::FSWAP_R;
|
|
|
|
|
if (dst < 4)
|
|
|
|
|
if (dst < RegisterCountFlt)
|
|
|
|
|
ibc.fdst = &f[dst];
|
|
|
|
|
else
|
|
|
|
|
ibc.fdst = &e[dst - 4];
|
|
|
|
|
ibc.fdst = &e[dst - RegisterCountFlt];
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(FADD_R) {
|
|
|
|
|
auto dst = instr.dst % 4;
|
|
|
|
|
auto src = instr.src % 4;
|
|
|
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
|
|
|
auto src = instr.src % RegisterCountFlt;
|
|
|
|
|
ibc.type = InstructionType::FADD_R;
|
|
|
|
|
ibc.fdst = &f[dst];
|
|
|
|
|
ibc.fsrc = &a[src];
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(FADD_M) {
|
|
|
|
|
auto dst = instr.dst % 4;
|
|
|
|
|
auto src = instr.src % 8;
|
|
|
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
|
|
|
auto src = instr.src % RegistersCount;
|
|
|
|
|
ibc.type = InstructionType::FADD_M;
|
|
|
|
|
ibc.fdst = &f[dst];
|
|
|
|
|
ibc.isrc = &r[src];
|
|
|
|
|
@ -706,16 +579,16 @@ namespace randomx {
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(FSUB_R) {
|
|
|
|
|
auto dst = instr.dst % 4;
|
|
|
|
|
auto src = instr.src % 4;
|
|
|
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
|
|
|
auto src = instr.src % RegisterCountFlt;
|
|
|
|
|
ibc.type = InstructionType::FSUB_R;
|
|
|
|
|
ibc.fdst = &f[dst];
|
|
|
|
|
ibc.fsrc = &a[src];
|
|
|
|
|
} break;
|
|
|
|
|
|
|
|
|
|
CASE_REP(FSUB_M) {
|
|
|
|
|
auto dst = instr.dst % 4;
|
|
|
|
|
auto src = instr.src % 8;
|
|
|
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
|
|
|
auto src = instr.src % RegistersCount;
|
|
|
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ibc.type = InstructionType::FSUB_M;
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ibc.fdst = &f[dst];
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ibc.isrc = &r[src];
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@ -724,22 +597,22 @@ namespace randomx {
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} break;
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CASE_REP(FSCAL_R) {
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auto dst = instr.dst % 4;
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auto dst = instr.dst % RegisterCountFlt;
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ibc.fdst = &f[dst];
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ibc.type = InstructionType::FSCAL_R;
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} break;
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CASE_REP(FMUL_R) {
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auto dst = instr.dst % 4;
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auto src = instr.src % 4;
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auto dst = instr.dst % RegisterCountFlt;
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auto src = instr.src % RegisterCountFlt;
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ibc.type = InstructionType::FMUL_R;
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ibc.fdst = &e[dst];
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ibc.fsrc = &a[src];
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} break;
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CASE_REP(FDIV_M) {
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auto dst = instr.dst % 4;
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auto src = instr.src % 8;
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auto dst = instr.dst % RegisterCountFlt;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::FDIV_M;
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ibc.fdst = &e[dst];
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ibc.isrc = &r[src];
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@ -748,7 +621,7 @@ namespace randomx {
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} break;
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CASE_REP(FSQRT_R) {
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auto dst = instr.dst % 4;
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auto dst = instr.dst % RegisterCountFlt;
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ibc.type = InstructionType::FSQRT_R;
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ibc.fdst = &e[dst];
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} break;
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@ -766,13 +639,13 @@ namespace randomx {
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ibc.target = registerUsage[reg];
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ibc.shift = instr.getModShift();
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ibc.creg = &r[reg];
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for (unsigned j = 0; j < 8; ++j) { //mark all registers as used
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for (unsigned j = 0; j < RegistersCount; ++j) { //mark all registers as used
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registerUsage[j] = i;
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}
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} break;
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CASE_REP(CFROUND) {
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auto src = instr.src % 8;
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auto src = instr.src % RegistersCount;
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ibc.isrc = &r[src];
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ibc.type = InstructionType::CFROUND;
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ibc.imm = instr.getImm32() & 63;
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tevador
5 years ago