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@ -33,7 +33,6 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#ifdef STATS
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#include <algorithm>
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#endif
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#include "divideByConstantCodegen.h"
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#ifdef FPUCHECK
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constexpr bool fpuCheck = true;
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@ -136,25 +135,23 @@ namespace RandomX {
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} break;
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case InstructionType::IDIV_C: {
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if (ibc.signedMultiplier != 0) {
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int_reg_t dividend = *ibc.idst;
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int_reg_t quotient = dividend >> ibc.preShift;
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if (ibc.increment) {
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quotient = quotient == UINT64_MAX ? UINT64_MAX : quotient + 1;
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}
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quotient = mulh(quotient, ibc.signedMultiplier);
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quotient >>= ibc.postShift;
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uint64_t dividend = *ibc.idst;
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uint64_t quotient = dividend / ibc.imm;
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*ibc.idst += quotient;
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} break;
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case InstructionType::ISDIV_C: {
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if (ibc.simm != -1) {
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int64_t dividend = unsigned64ToSigned2sCompl(*ibc.idst);
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int64_t quotient = dividend / ibc.simm;
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*ibc.idst += quotient;
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}
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else {
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*ibc.idst += *ibc.idst >> ibc.shift;
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uint64_t quotient = ~(*ibc.idst) + 1;
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*ibc.idst += quotient;
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}
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} break;
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case InstructionType::ISDIV_C: {
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} break;
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case InstructionType::INEG_R: {
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*ibc.idst = ~(*ibc.idst) + 1; //two's complement negative
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} break;
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@ -204,8 +201,8 @@ namespace RandomX {
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} break;
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case InstructionType::FSCAL_R: {
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const __m128d signMask = _mm_castsi128_pd(_mm_set1_epi64x(0x81F0000000000000));
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*ibc.fdst = _mm_xor_pd(*ibc.fdst, signMask);
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const __m128d mask = _mm_castsi128_pd(_mm_set1_epi64x(0x81F0000000000000));
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*ibc.fdst = _mm_xor_pd(*ibc.fdst, mask);
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} break;
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case InstructionType::FMUL_R: {
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@ -516,20 +513,7 @@ namespace RandomX {
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auto dst = instr.dst % RegistersCount;
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ibc.type = InstructionType::IDIV_C;
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ibc.idst = &r[dst];
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if (divisor & (divisor - 1)) {
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magicu_info mi = compute_unsigned_magic_info(divisor, sizeof(uint64_t) * 8);
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ibc.signedMultiplier = mi.multiplier;
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ibc.preShift = mi.pre_shift;
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ibc.postShift = mi.post_shift;
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ibc.increment = mi.increment;
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}
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else {
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ibc.signedMultiplier = 0;
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int shift = 0;
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while (divisor >>= 1)
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++shift;
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ibc.shift = shift;
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}
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ibc.imm = divisor;
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}
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else {
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ibc.type = InstructionType::NOP;
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@ -537,7 +521,16 @@ namespace RandomX {
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} break;
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CASE_REP(ISDIV_C) {
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ibc.type = InstructionType::NOP;
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int32_t divisor = unsigned32ToSigned2sCompl(instr.imm32);
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if (divisor != 0) {
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auto dst = instr.dst % RegistersCount;
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ibc.type = InstructionType::ISDIV_C;
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ibc.idst = &r[dst];
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ibc.simm = divisor;
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}
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else {
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ibc.type = InstructionType::NOP;
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}
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} break;
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CASE_REP(INEG_R) {
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