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529 lines
16 KiB
529 lines
16 KiB
/*
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Copyright (c) 2018 tevador
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This file is part of RandomX.
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RandomX is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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RandomX is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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//#define TRACE
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#include "AssemblyGeneratorX86.hpp"
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#include "common.hpp"
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#include "reciprocal.h"
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#include "Program.hpp"
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namespace RandomX {
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static const char* regR[8] = { "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" };
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static const char* regR32[8] = { "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" };
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static const char* regFE[8] = { "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regF[4] = { "xmm0", "xmm1", "xmm2", "xmm3" };
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static const char* regE[4] = { "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regA[4] = { "xmm8", "xmm9", "xmm10", "xmm11" };
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static const char* fsumInstr[4] = { "paddb", "paddw", "paddd", "paddq" };
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static const char* regA4 = "xmm12";
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static const char* dblMin = "xmm13";
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static const char* absMask = "xmm14";
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static const char* signMask = "xmm15";
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static const char* regMx = "rbp";
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static const char* regIc = "rbx";
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static const char* regIc32 = "ebx";
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static const char* regIc8 = "bl";
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static const char* regDatasetAddr = "rdi";
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static const char* regScratchpadAddr = "rsi";
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void AssemblyGeneratorX86::generateProgram(Program& prog) {
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asmCode.str(std::string()); //clear
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for (unsigned i = 0; i < ProgramLength; ++i) {
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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//asmCode << std::endl;
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}
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}
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void AssemblyGeneratorX86::traceint(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush " << regR[instr.dst] << std::endl;
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}
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}
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void AssemblyGeneratorX86::traceflt(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush 0" << std::endl;
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}
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}
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void AssemblyGeneratorX86::tracenop(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush 0" << std::endl;
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}
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}
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void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) {
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asmCode << "\t; " << instr;
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auto generator = engine[instr.opcode];
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(this->*generator)(instr, i);
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}
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void AssemblyGeneratorX86::genAddressReg(Instruction& instr, const char* reg = "eax") {
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asmCode << "\tmov " << reg << ", " << regR32[instr.src] << std::endl;
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asmCode << "\tand " << reg << ", " << ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask) << std::endl;
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}
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void AssemblyGeneratorX86::genAddressRegDst(Instruction& instr, int maskAlign = 8) {
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asmCode << "\tmov eax" << ", " << regR32[instr.dst] << std::endl;
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asmCode << "\tand eax" << ", " << ((instr.mod % 4) ? (ScratchpadL1Mask & (-maskAlign)) : (ScratchpadL2Mask & (-maskAlign))) << std::endl;
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}
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int32_t AssemblyGeneratorX86::genAddressImm(Instruction& instr) {
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return (int32_t)instr.imm32 & ScratchpadL3Mask;
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\tadd " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\tadd " << regR[instr.dst] << ", " << (int32_t)instr.imm32 << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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void AssemblyGeneratorX86::h_IADD_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_RC(Instruction& instr, int i) {
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << std::showpos << (int32_t)instr.imm32 << std::noshowpos << "]" << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_ISUB_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\tsub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", " << (int32_t)instr.imm32 << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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void AssemblyGeneratorX86::h_ISUB_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_9C(Instruction& instr, int i) {
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.dst] << "*8" << std::showpos << (int32_t)instr.imm32 << std::noshowpos << "]" << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\timul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\timul " << regR[instr.dst] << ", " << (int32_t)instr.imm32 << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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void AssemblyGeneratorX86::h_IMUL_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//4 uOPs
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void AssemblyGeneratorX86::h_IMULH_R(Instruction& instr, int i) {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//5.75 uOPs
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void AssemblyGeneratorX86::h_IMULH_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr, "ecx");
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul qword ptr [rsi+rcx]" << std::endl;
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}
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else {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//4 uOPs
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void AssemblyGeneratorX86::h_ISMULH_R(Instruction& instr, int i) {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\timul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//5.75 uOPs
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void AssemblyGeneratorX86::h_ISMULH_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr, "ecx");
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\timul qword ptr [rsi+rcx]" << std::endl;
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}
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else {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\timul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_INEG_R(Instruction& instr, int i) {
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asmCode << "\tneg " << regR[instr.dst] << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IXOR_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\txor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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}
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else {
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asmCode << "\txor " << regR[instr.dst] << ", " << (int32_t)instr.imm32 << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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void AssemblyGeneratorX86::h_IXOR_M(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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genAddressReg(instr);
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asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
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}
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else {
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asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//1.75 uOPs
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void AssemblyGeneratorX86::h_IROR_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
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asmCode << "\tror " << regR[instr.dst] << ", cl" << std::endl;
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}
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else {
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asmCode << "\tror " << regR[instr.dst] << ", " << (instr.imm32 & 63) << std::endl;
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}
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traceint(instr);
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}
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//1.75 uOPs
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void AssemblyGeneratorX86::h_IROL_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl;
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asmCode << "\trol " << regR[instr.dst] << ", cl" << std::endl;
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}
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else {
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asmCode << "\trol " << regR[instr.dst] << ", " << (instr.imm32 & 63) << std::endl;
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}
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traceint(instr);
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}
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//2 uOPs
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void AssemblyGeneratorX86::h_IMUL_RCP(Instruction& instr, int i) {
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if (instr.imm32 != 0) {
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uint32_t divisor = instr.imm32;
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asmCode << "\tmov rax, " << reciprocal(instr.imm32) << std::endl;
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asmCode << "\timul " << regR[instr.dst] << ", rax" << std::endl;
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traceint(instr);
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}
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else {
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tracenop(instr);
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}
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}
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//~8.5 uOPs
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void AssemblyGeneratorX86::h_ISDIV_C(Instruction& instr, int i) {
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tracenop(instr);
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}
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//2 uOPs
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void AssemblyGeneratorX86::h_ISWAP_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\txchg " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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traceint(instr);
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}
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else {
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tracenop(instr);
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}
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}
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//1 uOPs
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void AssemblyGeneratorX86::h_FSWAP_R(Instruction& instr, int i) {
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asmCode << "\tshufpd " << regFE[instr.dst] << ", " << regFE[instr.dst] << ", 1" << std::endl;
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traceflt(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_FADD_R(Instruction& instr, int i) {
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instr.dst %= 4;
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instr.src %= 4;
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asmCode << "\taddpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
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//asmCode << "\t" << fsumInstr[instr.mod % 4] << " " << signMask << ", " << regF[instr.dst] << std::endl;
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traceflt(instr);
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}
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//5 uOPs
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void AssemblyGeneratorX86::h_FADD_M(Instruction& instr, int i) {
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instr.dst %= 4;
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genAddressReg(instr);
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asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
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asmCode << "\taddpd " << regF[instr.dst] << ", xmm12" << std::endl;
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traceflt(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_FSUB_R(Instruction& instr, int i) {
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instr.dst %= 4;
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instr.src %= 4;
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asmCode << "\tsubpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
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//asmCode << "\t" << fsumInstr[instr.mod % 4] << " " << signMask << ", " << regF[instr.dst] << std::endl;
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traceflt(instr);
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}
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//5 uOPs
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void AssemblyGeneratorX86::h_FSUB_M(Instruction& instr, int i) {
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instr.dst %= 4;
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genAddressReg(instr);
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asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
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asmCode << "\tsubpd " << regF[instr.dst] << ", xmm12" << std::endl;
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traceflt(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_FSCAL_R(Instruction& instr, int i) {
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instr.dst %= 4;
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asmCode << "\txorps " << regF[instr.dst] << ", " << signMask << std::endl;
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traceflt(instr);
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}
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//1 uOPs
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void AssemblyGeneratorX86::h_FMUL_R(Instruction& instr, int i) {
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instr.dst %= 4;
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instr.src %= 4;
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asmCode << "\tmulpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
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traceflt(instr);
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}
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//7 uOPs
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void AssemblyGeneratorX86::h_FMUL_M(Instruction& instr, int i) {
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instr.dst %= 4;
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genAddressReg(instr);
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asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
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asmCode << "\tandps xmm12, xmm14" << std::endl;
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asmCode << "\tmulpd " << regE[instr.dst] << ", xmm12" << std::endl;
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asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
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traceflt(instr);
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}
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//2 uOPs
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void AssemblyGeneratorX86::h_FDIV_R(Instruction& instr, int i) {
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instr.dst %= 4;
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instr.src %= 4;
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asmCode << "\tdivpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
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asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
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traceflt(instr);
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}
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//7 uOPs
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void AssemblyGeneratorX86::h_FDIV_M(Instruction& instr, int i) {
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instr.dst %= 4;
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genAddressReg(instr);
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asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
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asmCode << "\tandps xmm12, xmm13" << std::endl;
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asmCode << "\torps xmm12, xmm14" << std::endl;
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asmCode << "\tdivpd " << regE[instr.dst] << ", xmm12" << std::endl;
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traceflt(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_FSQRT_R(Instruction& instr, int i) {
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instr.dst %= 4;
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asmCode << "\tsqrtpd " << regE[instr.dst] << ", " << regE[instr.dst] << std::endl;
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traceflt(instr);
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}
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//6 uOPs
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void AssemblyGeneratorX86::h_CFROUND(Instruction& instr, int i) {
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asmCode << "\tmov rax, " << regR[instr.src] << std::endl;
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int rotate = (13 - (instr.imm32 & 63)) & 63;
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if (rotate != 0)
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asmCode << "\trol rax, " << rotate << std::endl;
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asmCode << "\tand eax, 24576" << std::endl;
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asmCode << "\tor eax, 40896" << std::endl;
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asmCode << "\tmov dword ptr [rsp-8], eax" << std::endl;
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asmCode << "\tldmxcsr dword ptr [rsp-8]" << std::endl;
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tracenop(instr);
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}
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static inline const char* condition(Instruction& instr) {
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switch ((instr.mod >> 2) & 7)
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{
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case 0:
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return "be";
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case 1:
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return "a";
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case 2:
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return "s";
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case 3:
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return "ns";
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case 4:
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return "o";
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case 5:
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return "no";
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case 6:
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return "l";
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case 7:
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return "ge";
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default:
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UNREACHABLE;
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}
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}
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//4 uOPs
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void AssemblyGeneratorX86::h_COND_R(Instruction& instr, int i) {
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|
asmCode << "\txor ecx, ecx" << std::endl;
|
|
asmCode << "\tcmp " << regR32[instr.src] << ", " << (int32_t)instr.imm32 << std::endl;
|
|
asmCode << "\tset" << condition(instr) << " cl" << std::endl;
|
|
asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
|
|
traceint(instr);
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|
}
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|
|
|
//6 uOPs
|
|
void AssemblyGeneratorX86::h_COND_M(Instruction& instr, int i) {
|
|
asmCode << "\txor ecx, ecx" << std::endl;
|
|
genAddressReg(instr);
|
|
asmCode << "\tcmp dword ptr [rsi+rax], " << (int32_t)instr.imm32 << std::endl;
|
|
asmCode << "\tset" << condition(instr) << " cl" << std::endl;
|
|
asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
|
|
traceint(instr);
|
|
}
|
|
|
|
//3 uOPs
|
|
void AssemblyGeneratorX86::h_ISTORE(Instruction& instr, int i) {
|
|
genAddressRegDst(instr);
|
|
asmCode << "\tmov qword ptr [rsi+rax], " << regR[instr.src] << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
//3 uOPs
|
|
void AssemblyGeneratorX86::h_FSTORE(Instruction& instr, int i) {
|
|
genAddressRegDst(instr, 16);
|
|
asmCode << "\tmovapd xmmword ptr [rsi+rax], " << regFE[instr.src] << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_NOP(Instruction& instr, int i) {
|
|
asmCode << "\tnop" << std::endl;
|
|
tracenop(instr);
|
|
}
|
|
|
|
#include "instructionWeights.hpp"
|
|
#define INST_HANDLE(x) REPN(&AssemblyGeneratorX86::h_##x, WT(x))
|
|
|
|
InstructionGenerator AssemblyGeneratorX86::engine[256] = {
|
|
//Integer
|
|
INST_HANDLE(IADD_R)
|
|
INST_HANDLE(IADD_M)
|
|
INST_HANDLE(IADD_RC)
|
|
INST_HANDLE(ISUB_R)
|
|
INST_HANDLE(ISUB_M)
|
|
INST_HANDLE(IMUL_9C)
|
|
INST_HANDLE(IMUL_R)
|
|
INST_HANDLE(IMUL_M)
|
|
INST_HANDLE(IMULH_R)
|
|
INST_HANDLE(IMULH_M)
|
|
INST_HANDLE(ISMULH_R)
|
|
INST_HANDLE(ISMULH_M)
|
|
INST_HANDLE(IMUL_RCP)
|
|
INST_HANDLE(ISDIV_C)
|
|
INST_HANDLE(INEG_R)
|
|
INST_HANDLE(IXOR_R)
|
|
INST_HANDLE(IXOR_M)
|
|
INST_HANDLE(IROR_R)
|
|
INST_HANDLE(IROL_R)
|
|
INST_HANDLE(ISWAP_R)
|
|
|
|
//Common floating point
|
|
INST_HANDLE(FSWAP_R)
|
|
|
|
//Floating point group F
|
|
INST_HANDLE(FADD_R)
|
|
INST_HANDLE(FADD_M)
|
|
INST_HANDLE(FSUB_R)
|
|
INST_HANDLE(FSUB_M)
|
|
INST_HANDLE(FSCAL_R)
|
|
|
|
//Floating point group E
|
|
INST_HANDLE(FMUL_R)
|
|
INST_HANDLE(FMUL_M)
|
|
INST_HANDLE(FDIV_R)
|
|
INST_HANDLE(FDIV_M)
|
|
INST_HANDLE(FSQRT_R)
|
|
|
|
//Control
|
|
INST_HANDLE(COND_R)
|
|
INST_HANDLE(COND_M)
|
|
INST_HANDLE(CFROUND)
|
|
|
|
INST_HANDLE(ISTORE)
|
|
INST_HANDLE(FSTORE)
|
|
|
|
INST_HANDLE(NOP)
|
|
};
|
|
} |