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562 lines
16 KiB
562 lines
16 KiB
/*
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Copyright (c) 2018 tevador
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This file is part of RandomX.
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RandomX is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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RandomX is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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//#define TRACE
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#include "AssemblyGeneratorX86.hpp"
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#include "Pcg32.hpp"
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#include "common.hpp"
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#include "instructions.hpp"
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namespace RandomX {
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static const char* regR[8] = { "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" };
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static const char* regR32[8] = { "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" };
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static const char* regF[8] = { "xmm8", "xmm9", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" };
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static const char* regMx = "rbp";
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static const char* regIc = "ebx";
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static const char* regIc8 = "bl";
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static const char* regStackBeginAddr = "rdi";
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static const char* regScratchpadAddr = "rsi";
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void AssemblyGeneratorX86::generateProgram(const void* seed) {
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asmCode.str(std::string()); //clear
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Pcg32 gen(seed);
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for (unsigned i = 0; i < sizeof(RegisterFile) / sizeof(Pcg32::result_type); ++i) {
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gen();
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}
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Instruction instr;
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for (unsigned i = 0; i < ProgramLength; ++i) {
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for (unsigned j = 0; j < sizeof(instr) / sizeof(Pcg32::result_type); ++j) {
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*(((uint32_t*)&instr) + j) = gen();
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}
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generateCode(instr, i);
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asmCode << std::endl;
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}
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if(ProgramLength > 0)
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asmCode << "\tjmp rx_i_0" << std::endl;
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}
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void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) {
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asmCode << "rx_i_" << i << ": ;" << instr.getName() << std::endl;
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asmCode << "\tdec " << regIc << std::endl;
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asmCode << "\tjz rx_finish" << std::endl;
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auto generator = engine[instr.opcode];
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(this->*generator)(instr, i);
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}
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void AssemblyGeneratorX86::genar(Instruction& instr, int i) {
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asmCode << "\txor " << regR[instr.rega % RegistersCount] << ", 0" << std::hex << instr.addra << "h" << std::dec << std::endl;
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asmCode << "\tmov ecx, " << regR32[instr.rega % RegistersCount] << std::endl;
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asmCode << "\ttest " << regIc8 << ", 63" << std::endl;
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asmCode << "\tjnz short rx_body_" << i << std::endl;
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switch (instr.loca & 3)
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{
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case 0:
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case 1:
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case 2:
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asmCode << "\tcall rx_read_l1" << std::endl;
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asmCode << "rx_body_" << i << ":" << std::endl;
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if ((instr.loca & 192) == 0)
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asmCode << "\txor " << regMx << ", rcx" << std::endl;
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asmCode << "\tand ecx, " << (ScratchpadL1 - 1) << std::endl;
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break;
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default: //3
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asmCode << "\tcall rx_read_l2" << std::endl;
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asmCode << "rx_body_" << i << ":" << std::endl;
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if ((instr.loca & 192) == 0)
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asmCode << "\txor " << regMx << ", rcx" << std::endl;
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asmCode << "\tand ecx, " << (ScratchpadL2 - 1) << std::endl;
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break;
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}
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asmCode << "\tmov rax, qword ptr [" << regScratchpadAddr << "+rcx*8]" << std::endl;
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}
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void AssemblyGeneratorX86::genaf(Instruction& instr, int i) {
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asmCode << "\txor " << regR[instr.rega % RegistersCount] << ", 0" << std::hex << instr.addra << "h" << std::dec << std::endl;
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asmCode << "\tmov ecx, " << regR32[instr.rega % RegistersCount] << std::endl;
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asmCode << "\ttest " << regIc8 << ", 63" << std::endl;
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asmCode << "\tjnz short rx_body_" << i << std::endl;
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switch (instr.loca & 3)
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{
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case 0:
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case 1:
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case 2:
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asmCode << "\tcall rx_read_l1" << std::endl;
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asmCode << "rx_body_" << i << ":" << std::endl;
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if((instr.loca & 192) == 0)
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asmCode << "\txor " << regMx << ", rcx" << std::endl;
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asmCode << "\tand ecx, " << (ScratchpadL1 - 1) << std::endl;
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break;
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default: //3
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asmCode << "\tcall rx_read_l2" << std::endl;
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asmCode << "rx_body_" << i << ":" << std::endl;
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if ((instr.loca & 192) == 0)
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asmCode << "\txor " << regMx << ", rcx" << std::endl;
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asmCode << "\tand ecx, " << (ScratchpadL2 - 1) << std::endl;
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break;
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}
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asmCode << "\tcvtdq2pd xmm0, qword ptr [" << regScratchpadAddr << "+rcx*8]" << std::endl;
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}
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void AssemblyGeneratorX86::genbr0(Instruction& instr, const char* instrx86) {
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switch (instr.locb & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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asmCode << "\tmov rcx, " << regR[instr.regb % RegistersCount] << std::endl;
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asmCode << "\t" << instrx86 << " rax, cl" << std::endl;
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return;
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default:
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asmCode << "\t" << instrx86 << " rax, " << (instr.imm8 & 63) << std::endl;;
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return;
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}
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}
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void AssemblyGeneratorX86::genbr1(Instruction& instr) {
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switch (instr.locb & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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asmCode << regR[instr.regb % RegistersCount] << std::endl;
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return;
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default:
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asmCode << instr.imm32 << std::endl;;
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return;
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}
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}
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void AssemblyGeneratorX86::genbr132(Instruction& instr) {
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switch (instr.locb & 7)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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asmCode << regR32[instr.regb % RegistersCount] << std::endl;
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return;
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default:
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asmCode << instr.imm32 << std::endl;;
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return;
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}
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}
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void AssemblyGeneratorX86::genbf(Instruction& instr, const char* instrx86) {
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asmCode << "\t" << instrx86 << " xmm0, " << regF[instr.regb % RegistersCount] << std::endl;
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}
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void AssemblyGeneratorX86::gencr(Instruction& instr, bool rax = true) {
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switch (instr.locc & 7)
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{
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case 0:
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if(rax)
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asmCode << "\tmov rcx, rax" << std::endl;
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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asmCode << "\tand eax, " << (ScratchpadL2 - 1) << std::endl;
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asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rax * 8], rcx" << std::endl;
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if (trace) {
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asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], rcx" << std::endl;
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}
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return;
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case 1:
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case 2:
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case 3:
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if (rax)
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asmCode << "\tmov rcx, rax" << std::endl;
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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asmCode << "\tand eax, " << (ScratchpadL1 - 1) << std::endl;
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asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + rax * 8], rcx" << std::endl;
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if (trace) {
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asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], rcx" << std::endl;
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}
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return;
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default:
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asmCode << "\tmov " << regR[instr.regc % RegistersCount] << ", " << (rax ? "rax" : "rcx") << std::endl;
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if (trace) {
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asmCode << "\tmov qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], " << (rax ? "rax" : "rcx") << std::endl;
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}
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return;
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}
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}
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void AssemblyGeneratorX86::gencf(Instruction& instr, bool move = true) {
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if(move)
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asmCode << "\tmovaps " << regF[instr.regc % RegistersCount] << ", xmm0" << std::endl;
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const char* store = (instr.locc & 128) ? "movhpd" : "movlpd";
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switch (instr.locc & 7)
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{
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case 4:
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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asmCode << "\tand eax, " << (ScratchpadL2 - 1) << std::endl;
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asmCode << "\t" << store << " qword ptr [" << regScratchpadAddr << " + rax * 8], " << regF[instr.regc % RegistersCount] << std::endl;
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break;
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case 5:
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case 6:
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case 7:
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asmCode << "\tmov eax, " << regR32[instr.regc % RegistersCount] << std::endl;
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asmCode << "\txor eax, 0" << std::hex << instr.addrc << "h" << std::dec << std::endl;
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asmCode << "\tand eax, " << (ScratchpadL1 - 1) << std::endl;
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asmCode << "\t" << store << " qword ptr [" << regScratchpadAddr << " + rax * 8], " << regF[instr.regc % RegistersCount] << std::endl;
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break;
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}
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if (trace) {
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asmCode << "\t" << store << " qword ptr [" << regScratchpadAddr << " + " << regIc << " * 8 + 262136], " << regF[instr.regc % RegistersCount] << std::endl;
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}
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}
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void AssemblyGeneratorX86::h_ADD_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tadd rax, ";
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genbr1(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_ADD_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tadd eax, ";
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genbr132(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_SUB_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tsub rax, ";
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genbr1(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_SUB_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tsub eax, ";
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genbr132(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_MUL_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\timul rax, ";
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if ((instr.locb & 7) >= 6) {
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asmCode << "rax, ";
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}
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genbr1(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_MULH_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmov rcx, ";
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genbr1(instr);
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asmCode << "\tmul rcx" << std::endl;
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asmCode << "\tmov rax, rdx" << std::endl;
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_MUL_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmov ecx, eax" << std::endl;
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asmCode << "\tmov eax, ";
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genbr132(instr);
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asmCode << "\timul rax, rcx" << std::endl;
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_IMUL_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmovsxd rcx, eax" << std::endl;
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if ((instr.locb & 7) >= 6) {
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asmCode << "\tmov rax, " << instr.imm32 << std::endl;
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}
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else {
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asmCode << "\tmovsxd rax, " << regR32[instr.regb % RegistersCount] << std::endl;
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}
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asmCode << "\timul rax, rcx" << std::endl;
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_IMULH_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmov rcx, ";
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genbr1(instr);
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asmCode << "\timul rcx" << std::endl;
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asmCode << "\tmov rax, rdx" << std::endl;
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_DIV_64(Instruction& instr, int i) {
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genar(instr, i);
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if ((instr.locb & 7) >= 6) {
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if (instr.imm32 == 0) {
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asmCode << "\tmov ecx, 1" << std::endl;
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}
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else {
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asmCode << "\tmov ecx, " << instr.imm32 << std::endl;
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}
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}
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else {
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asmCode << "\tmov ecx, 1" << std::endl;
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asmCode << "\tmov edx, " << regR32[instr.regb % RegistersCount] << std::endl;
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asmCode << "\ttest edx, edx" << std::endl;
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asmCode << "\tcmovne ecx, edx" << std::endl;
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}
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asmCode << "\txor edx, edx" << std::endl;
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asmCode << "\tdiv rcx" << std::endl;
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_IDIV_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmov edx, ";
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genbr132(instr);
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asmCode << "\tcmp edx, -1" << std::endl;
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asmCode << "\tjne short safe_idiv_" << i << std::endl;
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asmCode << "\tmov rcx, rax" << std::endl;
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asmCode << "\trol rcx, 1" << std::endl;
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asmCode << "\tdec rcx" << std::endl;
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asmCode << "\tjz short result_idiv_" << i << std::endl;
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asmCode << "safe_idiv_" << i << ":" << std::endl;
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asmCode << "\tmov ecx, 1" << std::endl;
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asmCode << "\ttest edx, edx" << std::endl;
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asmCode << "\tcmovne ecx, edx" << std::endl;
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asmCode << "\tmovsxd rcx, ecx" << std::endl;
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asmCode << "\tcqo" << std::endl;
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asmCode << "\tidiv rcx" << std::endl;
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asmCode << "result_idiv_" << i << ":" << std::endl;
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_AND_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tand rax, ";
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genbr1(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_AND_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tand eax, ";
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genbr132(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_OR_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tor rax, ";
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genbr1(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_OR_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tor eax, ";
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genbr132(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_XOR_64(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\txor rax, ";
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genbr1(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_XOR_32(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\txor eax, ";
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genbr132(instr);
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_SHL_64(Instruction& instr, int i) {
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genar(instr, i);
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genbr0(instr, "shl");
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_SHR_64(Instruction& instr, int i) {
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genar(instr, i);
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genbr0(instr, "shr");
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_SAR_64(Instruction& instr, int i) {
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genar(instr, i);
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genbr0(instr, "sar");
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_ROL_64(Instruction& instr, int i) {
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genar(instr, i);
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genbr0(instr, "rol");
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_ROR_64(Instruction& instr, int i) {
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genar(instr, i);
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genbr0(instr, "ror");
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gencr(instr);
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}
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void AssemblyGeneratorX86::h_FPADD(Instruction& instr, int i) {
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genaf(instr, i);
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genbf(instr, "addpd");
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gencf(instr);
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}
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void AssemblyGeneratorX86::h_FPSUB(Instruction& instr, int i) {
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genaf(instr, i);
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genbf(instr, "subpd");
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gencf(instr);
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}
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void AssemblyGeneratorX86::h_FPMUL(Instruction& instr, int i) {
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genaf(instr, i);
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genbf(instr, "mulpd");
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asmCode << "\tmovaps xmm1, xmm0" << std::endl;
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asmCode << "\tcmpeqpd xmm1, xmm1" << std::endl;
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asmCode << "\tandps xmm0, xmm1" << std::endl;
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gencf(instr);
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}
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void AssemblyGeneratorX86::h_FPDIV(Instruction& instr, int i) {
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genaf(instr, i);
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genbf(instr, "divpd");
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asmCode << "\tmovaps xmm1, xmm0" << std::endl;
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asmCode << "\tcmpeqpd xmm1, xmm1" << std::endl;
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asmCode << "\tandps xmm0, xmm1" << std::endl;
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gencf(instr);
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}
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void AssemblyGeneratorX86::h_FPSQRT(Instruction& instr, int i) {
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genaf(instr, i);
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asmCode << "\tandps xmm0, xmm10" << std::endl;
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asmCode << "\tsqrtpd " << regF[instr.regc % RegistersCount] << ", xmm0" << std::endl;
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gencf(instr, false);
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}
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|
|
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void AssemblyGeneratorX86::h_FPROUND(Instruction& instr, int i) {
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genar(instr, i);
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asmCode << "\tmov rcx, rax" << std::endl;
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int rotate = (13 - (instr.imm8 & 63)) & 63;
|
|
if (rotate != 0)
|
|
asmCode << "\trol rax, " << rotate << std::endl;
|
|
asmCode << "\tand eax, 24576" << std::endl;
|
|
asmCode << "\tor eax, 40896" << std::endl;
|
|
asmCode << "\tmov dword ptr [rsp - 8], eax" << std::endl;
|
|
asmCode << "\tldmxcsr dword ptr [rsp - 8]" << std::endl;
|
|
gencr(instr, false);
|
|
}
|
|
|
|
static inline const char* jumpCondition(Instruction& instr, bool invert = false) {
|
|
switch ((instr.locb & 7) ^ invert)
|
|
{
|
|
case 0:
|
|
return "jbe";
|
|
case 1:
|
|
return "ja";
|
|
case 2:
|
|
return "js";
|
|
case 3:
|
|
return "jns";
|
|
case 4:
|
|
return "jo";
|
|
case 5:
|
|
return "jno";
|
|
case 6:
|
|
return "jl";
|
|
case 7:
|
|
return "jge";
|
|
}
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_JUMP(Instruction& instr, int i) {
|
|
genar(instr, i);
|
|
gencr(instr);
|
|
asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
|
|
asmCode << "\t" << jumpCondition(instr);
|
|
asmCode << " rx_i_" << wrapInstr(i + (instr.imm8 & 127) + 2) << std::endl;
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_CALL(Instruction& instr, int i) {
|
|
genar(instr, i);
|
|
gencr(instr);
|
|
asmCode << "\tcmp " << regR32[instr.regb % RegistersCount] << ", " << instr.imm32 << std::endl;
|
|
asmCode << "\t" << jumpCondition(instr, true);
|
|
asmCode << " short rx_i_" << wrapInstr(i + 1) << std::endl;
|
|
asmCode << "\tcall rx_i_" << wrapInstr(i + (instr.imm8 & 127) + 2) << std::endl;
|
|
}
|
|
|
|
void AssemblyGeneratorX86::h_RET(Instruction& instr, int i) {
|
|
genar(instr, i);
|
|
gencr(instr);
|
|
asmCode << "\tcmp rsp, " << regStackBeginAddr << std::endl;
|
|
asmCode << "\tje short rx_i_" << wrapInstr(i + 1) << std::endl;
|
|
asmCode << "\tret" << std::endl;
|
|
}
|
|
|
|
#include "instructionWeights.hpp"
|
|
#define INST_HANDLE(x) REPN(&AssemblyGeneratorX86::h_##x, WT(x))
|
|
|
|
InstructionGenerator AssemblyGeneratorX86::engine[256] = {
|
|
INST_HANDLE(ADD_64)
|
|
INST_HANDLE(ADD_32)
|
|
INST_HANDLE(SUB_64)
|
|
INST_HANDLE(SUB_32)
|
|
INST_HANDLE(MUL_64)
|
|
INST_HANDLE(MULH_64)
|
|
INST_HANDLE(MUL_32)
|
|
INST_HANDLE(IMUL_32)
|
|
INST_HANDLE(IMULH_64)
|
|
INST_HANDLE(DIV_64)
|
|
INST_HANDLE(IDIV_64)
|
|
INST_HANDLE(AND_64)
|
|
INST_HANDLE(AND_32)
|
|
INST_HANDLE(OR_64)
|
|
INST_HANDLE(OR_32)
|
|
INST_HANDLE(XOR_64)
|
|
INST_HANDLE(XOR_32)
|
|
INST_HANDLE(SHL_64)
|
|
INST_HANDLE(SHR_64)
|
|
INST_HANDLE(SAR_64)
|
|
INST_HANDLE(ROL_64)
|
|
INST_HANDLE(ROR_64)
|
|
INST_HANDLE(FPADD)
|
|
INST_HANDLE(FPSUB)
|
|
INST_HANDLE(FPMUL)
|
|
INST_HANDLE(FPDIV)
|
|
INST_HANDLE(FPSQRT)
|
|
INST_HANDLE(FPROUND)
|
|
INST_HANDLE(JUMP)
|
|
INST_HANDLE(CALL)
|
|
INST_HANDLE(RET)
|
|
};
|
|
} |