Commit Graph

26 Commits (d7eefce583550d27e211bb127dcd7f8ef903be1d)

Author SHA1 Message Date
tevador d9bc6cfeda Updated JIT compiler and assembly generator for new int -> float conversion
5 years ago
tevador 923420f0a3 Fixed mining and verification mode not giving the same results
5 years ago
tevador a145caa185 Fixed JIT compiler not producing the same code as genAsm and genNative
5 years ago
tevador 32d827d0a6 Interpreter with bytecode
5 years ago
tevador a586751f6b Removed FPNEG instruction
5 years ago
tevador 20eb549725 Merged load/store of integer and FP registers
5 years ago
tevador 8f2abd6c05 NOP instruction
5 years ago
tevador 005c67f64c Added explicit STORE instructions
5 years ago
tevador d2cb086221 ASM code generator for "small" programs that fit into the uOP cache
5 years ago
tevador 4fb168e249 Large page support for cache
5 years ago
tevador a7ffe8c19a Mix dataset cacheline with registers r0-r7
6 years ago
tevador 67e741ff22 Reduced x86 code size by 512 bytes (and ecx -> and eax)
6 years ago
tevador d1a808643d Random accesses - JIT compiler
6 years ago
tevador b71e0eec65 Optimizations to reduce code size under 32K
6 years ago
tevador 2f6a599ff6 Inlined calls for memory read
6 years ago
tevador 6519fed4d1 Combined prefetch + read into a single step
6 years ago
tevador 4189e4ebc6 Original number of VM instructions
6 years ago
tevador 619bee5418 Random dataset accesses - asm only
6 years ago
tevador 3caecc7646 Vector FPU instructions
6 years ago
tevador a09bee8d60 js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up)
6 years ago
tevador 55afe9646f Debuggable assembly generator
6 years ago
tevador ed0bc906d6 JIT compiler for x86
6 years ago
tevador ddc29cb4d3 Optimized x86 initialization
6 years ago
tevador 4f276541d2 Modified x86 register allocation
6 years ago
tevador 6332831ec1 Implemented cache shift
6 years ago
tevador cb0721056a Assembly code generator for Windows 64-bit
6 years ago