tevador
1276d67d2f
Fix build on Cygwin/MinGW
5 years ago
tevador
2b3a03a9dc
Fixed FSCAL instruction causing group F registers to exceed their intended maximum value
5 years ago
tevador
c1314dc2a2
Use values from configuration.h in assembly code
5 years ago
tevador
a22e3b3cb0
30% faster JIT compiler
5 years ago
tevador
ca96270509
Group E exponent changed from a static value (-240) to dynamic
5 years ago
tevador
7f6bdd9a52
Code cleanup & refactoring
5 years ago
tevador
270a4f97fe
Dataset size increased to 2080 MiB
...
Implemented dataset base offset
Tweaked SuperscalarHash constants to prevent register collisions
5 years ago
tevador
41b51a4858
Cleaned up legacy code
5 years ago
tevador
2e68c89740
Separate executeSuperscalar function
...
Tweaked superscalar hash constants
5 years ago
tevador
2132e5fef5
SuperscalarHash interpreter
...
Linux assembly code
5 years ago
tevador
6e3136b37f
Fixed cache alignment
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Performance tuning
5 years ago
tevador
77dbe14658
SuperscalarHash JIT compiler
...
(unfinished)
5 years ago
tevador
107270d93d
Reduced Dataset size to 2 GiB with 8 memory accesses per block
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Disabled Dataset growth
5 years ago
tevador
28ed776fbe
Light JIT compiler - Linux
5 years ago
tevador
73a11f5c01
CompiledLightVirtualMachine
5 years ago
tevador
6b344b81fd
initBlock asm version (disabled)
5 years ago
tevador
344f365c42
Updated constants according to the specs
5 years ago
tevador
d9bc6cfeda
Updated JIT compiler and assembly generator for new int -> float conversion
5 years ago
tevador
f76e8c2e20
Reworked "FNEG" instruction to make ASIC optimizations more difficult
5 years ago
tevador
69764966c0
Position independent loads fixed #21
5 years ago
tevador
32d827d0a6
Interpreter with bytecode
...
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
5 years ago
tevador
a586751f6b
Removed FPNEG instruction
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Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
5 years ago
tevador
1ee94bef2a
Added ISWAP instruction
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Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
5 years ago
tevador
20eb549725
Merged load/store of integer and FP registers
6 years ago
tevador
8f2abd6c05
NOP instruction
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register load/store from L3
6 years ago
tevador
005c67f64c
Added explicit STORE instructions
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JIT compiler
6 years ago
tevador
bd0dba88a8
4 scratchpad segments
6 years ago
tevador
a7ffe8c19a
Mix dataset cacheline with registers r0-r7
6 years ago
tevador
67e741ff22
Reduced x86 code size by 512 bytes (and ecx -> and eax)
6 years ago
tevador
d1a808643d
Random accesses - JIT compiler
6 years ago
tevador
b6d654291f
90 address transformations
6 years ago
tevador
3caecc7646
Vector FPU instructions
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JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
6 years ago