tevador
2132e5fef5
SuperscalarHash interpreter
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Linux assembly code
5 years ago
tevador
77dbe14658
SuperscalarHash JIT compiler
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(unfinished)
5 years ago
tevador
59bbb572c2
WIP
5 years ago
tevador
958d2bdc15
Fixed non-portable deserialization
5 years ago
tevador
f3b114af88
Replaced division instructions with IMUL_RCP
5 years ago
tevador
f76e8c2e20
Reworked "FNEG" instruction to make ASIC optimizations more difficult
5 years ago
tevador
32d827d0a6
Interpreter with bytecode
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Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
5 years ago
tevador
a586751f6b
Removed FPNEG instruction
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Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
5 years ago
tevador
ac4462ad42
Renamed floating point instructions
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Fixed negative source operand for FMUL_M and FDIV_M
5 years ago
tevador
1ee94bef2a
Added ISWAP instruction
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Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
5 years ago
tevador
8f2abd6c05
NOP instruction
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register load/store from L3
5 years ago
tevador
005c67f64c
Added explicit STORE instructions
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JIT compiler
5 years ago
tevador
d2cb086221
ASM code generator for "small" programs that fit into the uOP cache
5 years ago
tevador
1db7dd6e8b
Renamed immediate constants
6 years ago
tevador
6332831ec1
Implemented cache shift
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Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
6 years ago
tevador
cb0721056a
Assembly code generator for Windows 64-bit
6 years ago