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@ -45,7 +45,7 @@ namespace RandomX {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << imm32 << std::endl;
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os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
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}
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}
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@ -63,7 +63,7 @@ namespace RandomX {
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}
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void Instruction::h_IADD_RC(std::ostream& os) const {
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os << "r" << (int)dst << ", r" << (int)src << ", " << imm32 << std::endl;
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os << "r" << (int)dst << ", r" << (int)src << ", " << (int32_t)imm32 << std::endl;
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}
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//1 uOP
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@ -72,7 +72,7 @@ namespace RandomX {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << imm32 << std::endl;
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os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
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}
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}
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@ -90,7 +90,7 @@ namespace RandomX {
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}
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void Instruction::h_IMUL_9C(std::ostream& os) const {
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os << "r" << (int)dst << ", " << imm32 << std::endl;
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os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
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}
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void Instruction::h_IMUL_R(std::ostream& os) const {
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@ -98,7 +98,7 @@ namespace RandomX {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << imm32 << std::endl;
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os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
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}
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}
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@ -158,7 +158,7 @@ namespace RandomX {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << imm32 << std::endl;
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os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
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}
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}
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@ -194,11 +194,11 @@ namespace RandomX {
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}
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void Instruction::h_IDIV_C(std::ostream& os) const {
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os << "r" << (int)dst << ", " << (uint32_t)imm32 << std::endl;
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os << "r" << (int)dst << ", " << imm32 << std::endl;
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}
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void Instruction::h_ISDIV_C(std::ostream& os) const {
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os << "r" << (int)dst << ", " << imm32 << std::endl;
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os << "r" << (int)dst << ", " << (int32_t)imm32 << std::endl;
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}
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void Instruction::h_ISWAP_R(std::ostream& os) const {
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@ -300,13 +300,13 @@ namespace RandomX {
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}
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void Instruction::h_COND_R(std::ostream& os) const {
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os << "r" << (int)dst << ", " << condition((mod >> 2) & 7) << "(r" << (int)src << ", " << imm32 << ")" << std::endl;
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os << "r" << (int)dst << ", " << condition((mod >> 2) & 7) << "(r" << (int)src << ", " << (int32_t)imm32 << ")" << std::endl;
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}
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void Instruction::h_COND_M(std::ostream& os) const {
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os << "r" << (int)dst << ", " << condition((mod >> 2) & 7) << "(";
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genAddressReg(os);
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os << ", " << imm32 << ")" << std::endl;
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os << ", " << (int32_t)imm32 << ")" << std::endl;
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}
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void Instruction::h_ISTORE(std::ostream& os) const {
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