forked from wownero/wownero
jw
5 years ago
committed by
GitHub
commit
09bf93a931
@ -0,0 +1,39 @@
|
||||
# Maintainer: wowario <wowario at protonmail dot com>
|
||||
# Contributor: wowario <wowario at protonmail dot com>
|
||||
|
||||
pkgbase=('wownero-git')
|
||||
pkgname=('wownero-git')
|
||||
pkgver=0.5.0.2
|
||||
pkgrel=1
|
||||
pkgdesc="a fairly launched privacy-centric meme coin with no premine and a finite supply"
|
||||
license=('custom:Cryptonote')
|
||||
arch=('x86_64')
|
||||
url="http://wownero.org/"
|
||||
depends=('boost-libs' 'zeromq' 'unbound' 'libusb')
|
||||
makedepends=('git' 'cmake' 'boost')
|
||||
provides=('wownero-git')
|
||||
|
||||
source=("${pkgname}"::"git+https://github.com/wownero/wownero")
|
||||
|
||||
sha256sums=('SKIP')
|
||||
|
||||
pkgver() {
|
||||
cd "${srcdir}/${pkgname}"
|
||||
printf "$(echo ${pkgver} | sed 's/\.r.*//').r%s.g%s" \
|
||||
"$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
|
||||
}
|
||||
|
||||
build() {
|
||||
cd "${srcdir}/${pkgname}"
|
||||
git fetch --tags && git checkout tags/v0.5.0.2 -b v0.5.0.2
|
||||
USE_SINGLE_BUILDDIR=1 make
|
||||
}
|
||||
|
||||
package_wownero-git() {
|
||||
install -Dm644 "${srcdir}/${pkgname}/LICENSE" "${pkgdir}/usr/share/licenses/${pkgname}/LICENSE"
|
||||
install -Dm644 "${srcdir}/${pkgname}/utils/conf/wownerod.conf" "${pkgdir}/etc/wownerod.conf"
|
||||
install -Dm644 "${srcdir}/${pkgname}/utils/systemd/wownerod.service" "${pkgdir}/usr/lib/systemd/system/wownerod.service"
|
||||
install -Dm755 "${srcdir}/${pkgname}/build/release/bin/wownerod" "${pkgdir}/usr/bin/wownerod"
|
||||
install -Dm755 "${srcdir}/${pkgname}/build/release/bin/wownero-wallet-cli" "${pkgdir}/usr/bin/wownero-wallet-cli"
|
||||
install -Dm755 "${srcdir}/${pkgname}/build/release/bin/wownero-wallet-rpc" "${pkgdir}/usr/bin/wownero-wallet-rpc"
|
||||
}
|
||||
@ -1,8 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
if [ ! -d "$SNAP_USER_DATA/etc" ]; then
|
||||
mkdir $SNAP_USER_DATA/etc/
|
||||
cp -R $SNAP/etc/monerod.conf $SNAP_USER_DATA/etc/monerod.conf
|
||||
fi
|
||||
|
||||
exec "$SNAP/bin/monerod" "$@"
|
||||
|
Before Width: | Height: | Size: 1.5 KiB After Width: | Height: | Size: 18 KiB |
@ -0,0 +1,8 @@
|
||||
#!/bin/sh
|
||||
|
||||
if [ ! -d "$SNAP_USER_DATA/etc" ]; then
|
||||
mkdir $SNAP_USER_DATA/etc/
|
||||
cp -R $SNAP/etc/wownerod.conf $SNAP_USER_DATA/etc/wownerod.conf
|
||||
fi
|
||||
|
||||
exec "$SNAP/bin/wownerod" "$@"
|
||||
Binary file not shown.
@ -0,0 +1,425 @@
|
||||
#ifndef VARIANT4_RANDOM_MATH_H
|
||||
#define VARIANT4_RANDOM_MATH_H
|
||||
|
||||
// Register size can be configured to either 32 bit (uint32_t) or 64 bit (uint64_t)
|
||||
typedef uint32_t v4_reg;
|
||||
|
||||
enum V4_Settings
|
||||
{
|
||||
// Generate code with minimal theoretical latency = 45 cycles, which is equivalent to 15 multiplications
|
||||
TOTAL_LATENCY = 15 * 3,
|
||||
|
||||
// Always generate at least 60 instructions
|
||||
NUM_INSTRUCTIONS = 60,
|
||||
|
||||
// Available ALUs for MUL
|
||||
// Modern CPUs typically have only 1 ALU which can do multiplications
|
||||
ALU_COUNT_MUL = 1,
|
||||
|
||||
// Total available ALUs
|
||||
// Modern CPUs have 4 ALUs, but we use only 3 because random math executes together with other main loop code
|
||||
ALU_COUNT = 3,
|
||||
};
|
||||
|
||||
enum V4_InstructionList
|
||||
{
|
||||
MUL, // a*b
|
||||
ADD, // a+b + C, C is an unsigned 32-bit constant
|
||||
SUB, // a-b
|
||||
ROR, // rotate right "a" by "b & 31" bits
|
||||
ROL, // rotate left "a" by "b & 31" bits
|
||||
XOR, // a^b
|
||||
RET, // finish execution
|
||||
V4_INSTRUCTION_COUNT = RET,
|
||||
};
|
||||
|
||||
// V4_InstructionDefinition is used to generate code from random data
|
||||
// Every random sequence of bytes is a valid code
|
||||
//
|
||||
// There are 8 registers in total:
|
||||
// - 4 variable registers
|
||||
// - 4 constant registers initialized from loop variables
|
||||
//
|
||||
// This is why dst_index is 2 bits
|
||||
enum V4_InstructionDefinition
|
||||
{
|
||||
V4_OPCODE_BITS = 3,
|
||||
V4_DST_INDEX_BITS = 2,
|
||||
V4_SRC_INDEX_BITS = 3,
|
||||
};
|
||||
|
||||
struct V4_Instruction
|
||||
{
|
||||
uint8_t opcode;
|
||||
uint8_t dst_index;
|
||||
uint8_t src_index;
|
||||
uint32_t C;
|
||||
};
|
||||
|
||||
#ifndef FORCEINLINE
|
||||
#ifdef __GNUC__
|
||||
#define FORCEINLINE __attribute__((always_inline)) inline
|
||||
#elif _MSC_VER
|
||||
#define FORCEINLINE __forceinline
|
||||
#else
|
||||
#define FORCEINLINE inline
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef UNREACHABLE_CODE
|
||||
#ifdef __GNUC__
|
||||
#define UNREACHABLE_CODE __builtin_unreachable()
|
||||
#elif _MSC_VER
|
||||
#define UNREACHABLE_CODE __assume(false)
|
||||
#else
|
||||
#define UNREACHABLE_CODE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Random math interpreter's loop is fully unrolled and inlined to achieve 100% branch prediction on CPU:
|
||||
// every switch-case will point to the same destination on every iteration of Cryptonight main loop
|
||||
//
|
||||
// This is about as fast as it can get without using low-level machine code generation
|
||||
static FORCEINLINE void v4_random_math(const struct V4_Instruction* code, v4_reg* r)
|
||||
{
|
||||
enum
|
||||
{
|
||||
REG_BITS = sizeof(v4_reg) * 8,
|
||||
};
|
||||
|
||||
#define V4_EXEC(i) \
|
||||
{ \
|
||||
const struct V4_Instruction* op = code + i; \
|
||||
const v4_reg src = r[op->src_index]; \
|
||||
v4_reg* dst = r + op->dst_index; \
|
||||
switch (op->opcode) \
|
||||
{ \
|
||||
case MUL: \
|
||||
*dst *= src; \
|
||||
break; \
|
||||
case ADD: \
|
||||
*dst += src + op->C; \
|
||||
break; \
|
||||
case SUB: \
|
||||
*dst -= src; \
|
||||
break; \
|
||||
case ROR: \
|
||||
{ \
|
||||
const uint32_t shift = src % REG_BITS; \
|
||||
*dst = (*dst >> shift) | (*dst << ((REG_BITS - shift) % REG_BITS)); \
|
||||
} \
|
||||
break; \
|
||||
case ROL: \
|
||||
{ \
|
||||
const uint32_t shift = src % REG_BITS; \
|
||||
*dst = (*dst << shift) | (*dst >> ((REG_BITS - shift) % REG_BITS)); \
|
||||
} \
|
||||
break; \
|
||||
case XOR: \
|
||||
*dst ^= src; \
|
||||
break; \
|
||||
case RET: \
|
||||
return; \
|
||||
default: \
|
||||
UNREACHABLE_CODE; \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define V4_EXEC_10(j) \
|
||||
V4_EXEC(j + 0) \
|
||||
V4_EXEC(j + 1) \
|
||||
V4_EXEC(j + 2) \
|
||||
V4_EXEC(j + 3) \
|
||||
V4_EXEC(j + 4) \
|
||||
V4_EXEC(j + 5) \
|
||||
V4_EXEC(j + 6) \
|
||||
V4_EXEC(j + 7) \
|
||||
V4_EXEC(j + 8) \
|
||||
V4_EXEC(j + 9)
|
||||
|
||||
// Generated program can have 60 + a few more (usually 2-3) instructions to achieve required latency
|
||||
// I've checked all block heights < 10,000,000 and here is the distribution of program sizes:
|
||||
//
|
||||
// 60 28495
|
||||
// 61 106077
|
||||
// 62 2455855
|
||||
// 63 5114930
|
||||
// 64 1020868
|
||||
// 65 1109026
|
||||
// 66 151756
|
||||
// 67 8429
|
||||
// 68 4477
|
||||
// 69 87
|
||||
|
||||
// Unroll 70 instructions here
|
||||
V4_EXEC_10(0); // instructions 0-9
|
||||
V4_EXEC_10(10); // instructions 10-19
|
||||
V4_EXEC_10(20); // instructions 20-29
|
||||
V4_EXEC_10(30); // instructions 30-39
|
||||
V4_EXEC_10(40); // instructions 40-49
|
||||
V4_EXEC_10(50); // instructions 50-59
|
||||
V4_EXEC_10(60); // instructions 60-69
|
||||
|
||||
#undef V4_EXEC_10
|
||||
#undef V4_EXEC
|
||||
}
|
||||
|
||||
// If we don't have enough data available, generate more
|
||||
static FORCEINLINE void check_data(size_t* data_index, const size_t bytes_needed, int8_t* data, const size_t data_size)
|
||||
{
|
||||
if (*data_index + bytes_needed > data_size)
|
||||
{
|
||||
hash_extra_blake(data, data_size, (char*) data);
|
||||
*data_index = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// Generates as many random math operations as possible with given latency and ALU restrictions
|
||||
static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_t height)
|
||||
{
|
||||
// MUL is 3 cycles, 3-way addition and rotations are 2 cycles, SUB/XOR are 1 cycle
|
||||
// These latencies match real-life instruction latencies for Intel CPUs starting from Sandy Bridge and up to Skylake/Coffee lake
|
||||
//
|
||||
// AMD Ryzen has the same latencies except 1-cycle ROR/ROL, so it'll be a bit faster than Intel Sandy Bridge and newer processors
|
||||
// Surprisingly, Intel Nehalem also has 1-cycle ROR/ROL, so it'll also be faster than Intel Sandy Bridge and newer processors
|
||||
// AMD Bulldozer has 4 cycles latency for MUL (slower than Intel) and 1 cycle for ROR/ROL (faster than Intel), so average performance will be the same
|
||||
// Source: https://www.agner.org/optimize/instruction_tables.pdf
|
||||
const int op_latency[V4_INSTRUCTION_COUNT] = { 3, 2, 1, 2, 2, 1 };
|
||||
|
||||
// Instruction latencies for theoretical ASIC implementation
|
||||
const int asic_op_latency[V4_INSTRUCTION_COUNT] = { 3, 1, 1, 1, 1, 1 };
|
||||
|
||||
// Available ALUs for each instruction
|
||||
const int op_ALUs[V4_INSTRUCTION_COUNT] = { ALU_COUNT_MUL, ALU_COUNT, ALU_COUNT, ALU_COUNT, ALU_COUNT, ALU_COUNT };
|
||||
|
||||
int8_t data[32];
|
||||
memset(data, 0, sizeof(data));
|
||||
uint64_t tmp = SWAP64LE(height);
|
||||
memcpy(data, &tmp, sizeof(uint64_t));
|
||||
|
||||
// Set data_index past the last byte in data
|
||||
// to trigger full data update with blake hash
|
||||
// before we start using it
|
||||
size_t data_index = sizeof(data);
|
||||
|
||||
int code_size;
|
||||
do {
|
||||
int latency[8];
|
||||
int asic_latency[8];
|
||||
|
||||
// Tracks previous instruction and value of the source operand for registers R0-R3 throughout code execution
|
||||
// byte 0: current value of the destination register
|
||||
// byte 1: instruction opcode
|
||||
// byte 2: current value of the source register
|
||||
//
|
||||
// Registers R4-R7 are constant and are treated as having the same value because when we do
|
||||
// the same operation twice with two constant source registers, it can be optimized into a single operation
|
||||
uint32_t inst_data[8] = { 0, 1, 2, 3, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF };
|
||||
|
||||
bool alu_busy[TOTAL_LATENCY + 1][ALU_COUNT];
|
||||
bool is_rotation[V4_INSTRUCTION_COUNT];
|
||||
bool rotated[4];
|
||||
int rotate_count = 0;
|
||||
|
||||
memset(latency, 0, sizeof(latency));
|
||||
memset(asic_latency, 0, sizeof(asic_latency));
|
||||
memset(alu_busy, 0, sizeof(alu_busy));
|
||||
memset(is_rotation, 0, sizeof(is_rotation));
|
||||
memset(rotated, 0, sizeof(rotated));
|
||||
is_rotation[ROR] = true;
|
||||
is_rotation[ROL] = true;
|
||||
|
||||
int num_retries = 0;
|
||||
code_size = 0;
|
||||
|
||||
int total_iterations = 0;
|
||||
|
||||
// Generate random code to achieve minimal required latency for our abstract CPU
|
||||
// Try to get this latency for all 4 registers
|
||||
while (((latency[0] < TOTAL_LATENCY) || (latency[1] < TOTAL_LATENCY) || (latency[2] < TOTAL_LATENCY) || (latency[3] < TOTAL_LATENCY)) && (num_retries < 64))
|
||||
{
|
||||
// Fail-safe to guarantee loop termination
|
||||
++total_iterations;
|
||||
if (total_iterations > 256)
|
||||
break;
|
||||
|
||||
check_data(&data_index, 1, data, sizeof(data));
|
||||
|
||||
const uint8_t c = ((uint8_t*)data)[data_index++];
|
||||
|
||||
// MUL = opcodes 0-2
|
||||
// ADD = opcode 3
|
||||
// SUB = opcode 4
|
||||
// ROR/ROL = opcode 5, shift direction is selected randomly
|
||||
// XOR = opcodes 6-7
|
||||
uint8_t opcode = c & ((1 << V4_OPCODE_BITS) - 1);
|
||||
if (opcode == 5)
|
||||
{
|
||||
check_data(&data_index, 1, data, sizeof(data));
|
||||
opcode = (data[data_index++] >= 0) ? ROR : ROL;
|
||||
}
|
||||
else if (opcode >= 6)
|
||||
{
|
||||
opcode = XOR;
|
||||
}
|
||||
else
|
||||
{
|
||||
opcode = (opcode <= 2) ? MUL : (opcode - 2);
|
||||
}
|
||||
|
||||
uint8_t dst_index = (c >> V4_OPCODE_BITS) & ((1 << V4_DST_INDEX_BITS) - 1);
|
||||
uint8_t src_index = (c >> (V4_OPCODE_BITS + V4_DST_INDEX_BITS)) & ((1 << V4_SRC_INDEX_BITS) - 1);
|
||||
|
||||
const int a = dst_index;
|
||||
int b = src_index;
|
||||
|
||||
// Don't do ADD/SUB/XOR with the same register
|
||||
if (((opcode == ADD) || (opcode == SUB) || (opcode == XOR)) && (a == b))
|
||||
{
|
||||
// a is always < 4, so we don't need to check bounds here
|
||||
b = a + 4;
|
||||
src_index = b;
|
||||
}
|
||||
|
||||
// Don't do rotation with the same destination twice because it's equal to a single rotation
|
||||
if (is_rotation[opcode] && rotated[a])
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
// Don't do the same instruction (except MUL) with the same source value twice because all other cases can be optimized:
|
||||
// 2xADD(a, b, C) = ADD(a, b*2, C1+C2), same for SUB and rotations
|
||||
// 2xXOR(a, b) = NOP
|
||||
if ((opcode != MUL) && ((inst_data[a] & 0xFFFF00) == (opcode << 8) + ((inst_data[b] & 255) << 16)))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
// Find which ALU is available (and when) for this instruction
|
||||
int next_latency = (latency[a] > latency[b]) ? latency[a] : latency[b];
|
||||
int alu_index = -1;
|
||||
while (next_latency < TOTAL_LATENCY)
|
||||
{
|
||||
for (int i = op_ALUs[opcode] - 1; i >= 0; --i)
|
||||
{
|
||||
if (!alu_busy[next_latency][i])
|
||||
{
|
||||
// ADD is implemented as two 1-cycle instructions on a real CPU, so do an additional availability check
|
||||
if ((opcode == ADD) && alu_busy[next_latency + 1][i])
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
// Rotation can only start when previous rotation is finished, so do an additional availability check
|
||||
if (is_rotation[opcode] && (next_latency < rotate_count * op_latency[opcode]))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
alu_index = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (alu_index >= 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
++next_latency;
|
||||
}
|
||||
|
||||
// Don't generate instructions that leave some register unchanged for more than 7 cycles
|
||||
if (next_latency > latency[a] + 7)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
next_latency += op_latency[opcode];
|
||||
|
||||
if (next_latency <= TOTAL_LATENCY)
|
||||
{
|
||||
if (is_rotation[opcode])
|
||||
{
|
||||
++rotate_count;
|
||||
}
|
||||
|
||||
// Mark ALU as busy only for the first cycle when it starts executing the instruction because ALUs are fully pipelined
|
||||
alu_busy[next_latency - op_latency[opcode]][alu_index] = true;
|
||||
latency[a] = next_latency;
|
||||
|
||||
// ASIC is supposed to have enough ALUs to run as many independent instructions per cycle as possible, so latency calculation for ASIC is simple
|
||||
asic_latency[a] = ((asic_latency[a] > asic_latency[b]) ? asic_latency[a] : asic_latency[b]) + asic_op_latency[opcode];
|
||||
|
||||
rotated[a] = is_rotation[opcode];
|
||||
|
||||
inst_data[a] = code_size + (opcode << 8) + ((inst_data[b] & 255) << 16);
|
||||
|
||||
code[code_size].opcode = opcode;
|
||||
code[code_size].dst_index = dst_index;
|
||||
code[code_size].src_index = src_index;
|
||||
code[code_size].C = 0;
|
||||
|
||||
if (opcode == ADD)
|
||||
{
|
||||
// ADD instruction is implemented as two 1-cycle instructions on a real CPU, so mark ALU as busy for the next cycle too
|
||||
alu_busy[next_latency - op_latency[opcode] + 1][alu_index] = true;
|
||||
|
||||
// ADD instruction requires 4 more random bytes for 32-bit constant "C" in "a = a + b + C"
|
||||
check_data(&data_index, sizeof(uint32_t), data, sizeof(data));
|
||||
uint32_t t;
|
||||
memcpy(&t, data + data_index, sizeof(uint32_t));
|
||||
code[code_size].C = SWAP32LE(t);
|
||||
data_index += sizeof(uint32_t);
|
||||
}
|
||||
|
||||
++code_size;
|
||||
if (code_size >= NUM_INSTRUCTIONS)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
++num_retries;
|
||||
}
|
||||
}
|
||||
|
||||
// ASIC has more execution resources and can extract as much parallelism from the code as possible
|
||||
// We need to add a few more MUL and ROR instructions to achieve minimal required latency for ASIC
|
||||
// Get this latency for at least 1 of the 4 registers
|
||||
const int prev_code_size = code_size;
|
||||
while ((asic_latency[0] < TOTAL_LATENCY) && (asic_latency[1] < TOTAL_LATENCY) && (asic_latency[2] < TOTAL_LATENCY) && (asic_latency[3] < TOTAL_LATENCY))
|
||||
{
|
||||
int min_idx = 0;
|
||||
int max_idx = 0;
|
||||
for (int i = 1; i < 4; ++i)
|
||||
{
|
||||
if (asic_latency[i] < asic_latency[min_idx]) min_idx = i;
|
||||
if (asic_latency[i] > asic_latency[max_idx]) max_idx = i;
|
||||
}
|
||||
|
||||
const uint8_t pattern[3] = { ROR, MUL, MUL };
|
||||
const uint8_t opcode = pattern[(code_size - prev_code_size) % 3];
|
||||
latency[min_idx] = latency[max_idx] + op_latency[opcode];
|
||||
asic_latency[min_idx] = asic_latency[max_idx] + asic_op_latency[opcode];
|
||||
|
||||
code[code_size].opcode = opcode;
|
||||
code[code_size].dst_index = min_idx;
|
||||
code[code_size].src_index = max_idx;
|
||||
code[code_size].C = 0;
|
||||
++code_size;
|
||||
}
|
||||
|
||||
// There is ~99.8% chance that code_size >= NUM_INSTRUCTIONS here, so second iteration is required rarely
|
||||
} while (code_size < NUM_INSTRUCTIONS);
|
||||
|
||||
// Add final instruction to stop the interpreter
|
||||
code[code_size].opcode = RET;
|
||||
code[code_size].dst_index = 0;
|
||||
code[code_size].src_index = 0;
|
||||
code[code_size].C = 0;
|
||||
|
||||
return code_size;
|
||||
}
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,54 @@
|
||||
#!/usr/bin/perl
|
||||
|
||||
# BSD 3-Clause License
|
||||
#
|
||||
# Copyright (c) 2018, Karbowanec
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# * Redistributions of source code must retain the above copyright notice, this
|
||||
# list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
# * Neither the name of the copyright holder nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
# Returns timestamps and difficulty data for wownero (monero RPC)
|
||||
# Run: perl export_data.pl 50 300
|
||||
|
||||
$IP='explorer.wowne.ro:11181';
|
||||
$begin=$ARGV[0];
|
||||
if ($#ARGV == 1 ) { $end=$ARGV[1]; }
|
||||
else {
|
||||
$h=`curl -s -X POST http://$IP/json_rpc -d '{"params": {},"jsonrpc":"2.0","id":"test","method":"getblockcount"}' -H 'Content-Type: application/json'`;
|
||||
$h=~/"count"\D+(\d+)/sg;
|
||||
$end=$1;
|
||||
print "$end\n";
|
||||
}
|
||||
print "also printed to file\n\n";
|
||||
open (F,">wownero-data.txt");
|
||||
for ($i=$begin; $i<$end; $i++) {
|
||||
$k=qq(-d '{"params":{"height":$i},"jsonrpc":"2.0","id":"test","method":"getblockheaderbyheight"}' -H 'Content-Type: application/json');
|
||||
$k=`curl -s -X POST http://$IP/json_rpc $k`;
|
||||
$k=~/"difficulty"\D+(\d+).+"timestamp"\D+(\d+)/sg;
|
||||
($d, $t)=($1,$2);
|
||||
print "$i\t$t\t$d\n";
|
||||
print F "$i\t$t\t$d\n";
|
||||
|
||||
}
|
||||
close F;
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,86 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
# BSD 3-Clause License
|
||||
#
|
||||
# Copyright (c) 2018, Jason Rhinelander
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# * Redistributions of source code must retain the above copyright notice, this
|
||||
# list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
# * Neither the name of the copyright holder nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
import requests
|
||||
|
||||
# CONFIGURATION:
|
||||
|
||||
# Target time
|
||||
DIFFICULTY_TARGET = 300
|
||||
|
||||
# Range of blocks to analyze:
|
||||
N = 20
|
||||
|
||||
# Fork height/name pairs (purely cosmetic to indicate forks in the output)
|
||||
forks = {
|
||||
50: 'v12',
|
||||
}
|
||||
|
||||
# First element is the URL to fetch; the rest are keys to follow to get the current network height:
|
||||
api_height = ('http://explorer.wowne.ro:8082/api/networkinfo', 'data', 'height')
|
||||
|
||||
# First element is a format with {} to be replaced with the block height; the rest are keys to
|
||||
# follow to get that block's timestamp:
|
||||
api_block = ('http://explorer.wowne.ro:8082/api/block/{}', 'data', 'timestamp')
|
||||
|
||||
# Run: ./wow-emission
|
||||
|
||||
# END CONFIGURATION
|
||||
|
||||
time_period = N*DIFFICULTY_TARGET
|
||||
h = requests.get(api_height[0]).json()
|
||||
for i in api_height[1:]:
|
||||
h = h[i]
|
||||
|
||||
h -= 1 # want height of last block, not current network height
|
||||
|
||||
next_ts = None
|
||||
next_h = None
|
||||
while h > 1:
|
||||
contains_fork = None
|
||||
for fork_height, fork_name in forks.items():
|
||||
if h is not None and h < fork_height <= next_h:
|
||||
contains_fork = fork_name
|
||||
break
|
||||
|
||||
ts = requests.get(api_block[0].format(h)).json()
|
||||
for i in api_block[1:]:
|
||||
ts = ts[i]
|
||||
|
||||
if next_ts is not None:
|
||||
elapsed = next_ts - ts
|
||||
print("{} -- {}: elapsed time = {}s = {:.2f}% of {} target = avg solvetime = {:.2f} minutes over {} blocks".format(
|
||||
h, next_h, elapsed, 100.*elapsed/time_period, time_period, elapsed/60/N, N), end='')
|
||||
|
||||
print(" --- ({} FORK) ---".format(contains_fork) if contains_fork is not None else "")
|
||||
|
||||
next_ts = ts
|
||||
next_h = h
|
||||
h -= N
|
||||
@ -0,0 +1,478 @@
|
||||
50 1544807250 111
|
||||
51 1544807251 111
|
||||
52 1544807267 7120
|
||||
53 1544807942 15340
|
||||
54 1544808953 9094
|
||||
55 1544809140 5748
|
||||
56 1544809214 6054
|
||||
57 1544809224 6678
|
||||
58 1544809698 7557
|
||||
59 1544809817 7066
|
||||
60 1544809969 7524
|
||||
61 1544810017 7901
|
||||
62 1544810260 8566
|
||||
63 1544810847 8717
|
||||
64 1544811309 8063
|
||||
65 1544811461 7758
|
||||
66 1544812116 8017
|
||||
67 1544812450 7458
|
||||
68 1544812700 7412
|
||||
69 1544813448 7477
|
||||
70 1544813747 6956
|
||||
71 1544814796 6957
|
||||
72 1544815060 6287
|
||||
73 1544816309 6315
|
||||
74 1544816329 5670
|
||||
75 1544816563 5840
|
||||
76 1544816875 5881
|
||||
77 1544816886 5874
|
||||
78 1544817057 6046
|
||||
79 1544817102 6123
|
||||
80 1544817107 6278
|
||||
81 1544817697 6462
|
||||
82 1544818307 6286
|
||||
83 1544818405 6114
|
||||
84 1544818452 6222
|
||||
85 1544818601 6360
|
||||
86 1544818970 6443
|
||||
87 1544818977 6406
|
||||
88 1544819349 6563
|
||||
89 1544819355 6524
|
||||
90 1544819520 6680
|
||||
91 1544819607 6752
|
||||
92 1544819648 6866
|
||||
93 1544819784 7007
|
||||
94 1544819815 7097
|
||||
95 1544820138 7246
|
||||
96 1544820865 7234
|
||||
97 1544821319 7011
|
||||
98 1544821764 6935
|
||||
99 1544821949 6867
|
||||
100 1544821999 6920
|
||||
101 1544822103 7035
|
||||
102 1544822445 7127
|
||||
103 1544822499 7107
|
||||
104 1544822630 7220
|
||||
105 1544823113 7299
|
||||
106 1544823164 7216
|
||||
107 1544823207 7327
|
||||
108 1544823462 7443
|
||||
109 1544824390 7464
|
||||
110 1544824483 7194
|
||||
111 1544824693 7279
|
||||
112 1544825153 7316
|
||||
113 1544825447 7252
|
||||
114 1544826047 7254
|
||||
115 1544826816 7140
|
||||
116 1544826840 6970
|
||||
117 1544826893 7068
|
||||
118 1544827218 7155
|
||||
119 1544827246 7147
|
||||
120 1544827258 7243
|
||||
121 1544827533 7346
|
||||
122 1544827536 7353
|
||||
123 1544828070 7353
|
||||
124 1544828149 7459
|
||||
125 1544828183 7459
|
||||
126 1544828541 7374
|
||||
127 1544829151 7374
|
||||
128 1544829353 7451
|
||||
129 1544829375 7451
|
||||
130 1544829428 7545
|
||||
131 1544830618 7545
|
||||
132 1544830629 7522
|
||||
133 1544831213 7522
|
||||
134 1544831672 7414
|
||||
135 1544831917 7414
|
||||
136 1544831961 7447
|
||||
137 1544832296 7447
|
||||
138 1544833065 7542
|
||||
139 1544833372 7542
|
||||
140 1544833650 7624
|
||||
141 1544833856 7624
|
||||
142 1544834092 7335
|
||||
143 1544834232 7335
|
||||
144 1544834476 7428
|
||||
145 1544834789 7428
|
||||
146 1544834932 7428
|
||||
147 1544835167 7428
|
||||
148 1544835577 7428
|
||||
149 1544835658 7343
|
||||
150 1544835719 7296
|
||||
151 1544835874 7312
|
||||
152 1544836381 7388
|
||||
153 1544836763 7378
|
||||
154 1544838241 7247
|
||||
155 1544838310 7249
|
||||
156 1544838531 7258
|
||||
157 1544838683 7287
|
||||
158 1544838835 7306
|
||||
159 1544838915 7349
|
||||
160 1544838937 7364
|
||||
161 1544839139 7360
|
||||
162 1544839632 7402
|
||||
163 1544839639 7419
|
||||
164 1544839766 7390
|
||||
165 1544840188 7449
|
||||
166 1544840324 7509
|
||||
167 1544840725 7549
|
||||
168 1544841073 7493
|
||||
169 1544841395 7470
|
||||
170 1544841881 7184
|
||||
171 1544841925 7238
|
||||
172 1544842032 7255
|
||||
173 1544842532 7288
|
||||
174 1544842689 7325
|
||||
175 1544842741 7375
|
||||
176 1544842993 7439
|
||||
177 1544843611 7461
|
||||
178 1544843765 7418
|
||||
179 1544843882 7485
|
||||
180 1544843949 7530
|
||||
181 1544844471 7501
|
||||
182 1544846276 7538
|
||||
183 1544847445 7518
|
||||
184 1544848223 7506
|
||||
185 1544848650 7500
|
||||
186 1544849293 7456
|
||||
187 1544849307 7451
|
||||
188 1544849402 7504
|
||||
189 1544849696 7602
|
||||
190 1544849805 7623
|
||||
191 1544850606 7640
|
||||
192 1544850744 7592
|
||||
193 1544851386 7559
|
||||
194 1544851652 7554
|
||||
195 1544851664 7562
|
||||
196 1544851719 7554
|
||||
197 1544852399 7483
|
||||
198 1544853145 7216
|
||||
199 1544853804 7070
|
||||
200 1544853963 6948
|
||||
201 1544854234 6987
|
||||
202 1544854678 6928
|
||||
203 1544854843 6973
|
||||
204 1544854969 7100
|
||||
205 1544855088 7107
|
||||
206 1544855298 7303
|
||||
207 1544855399 7204
|
||||
208 1544855417 7448
|
||||
209 1544855575 7332
|
||||
210 1544855609 7340
|
||||
211 1544855796 7418
|
||||
212 1544855904 7423
|
||||
213 1544856100 7328
|
||||
214 1544856230 7195
|
||||
215 1544856308 7073
|
||||
216 1544856344 7161
|
||||
217 1544856487 7234
|
||||
218 1544856585 7172
|
||||
219 1544856616 7155
|
||||
220 1544856803 7166
|
||||
221 1544857509 7221
|
||||
222 1544857649 7188
|
||||
223 1544857660 7247
|
||||
224 1544857833 7252
|
||||
225 1544857938 7259
|
||||
226 1544858083 7275
|
||||
227 1544858344 7250
|
||||
228 1544858447 7259
|
||||
229 1544858893 7228
|
||||
230 1544858949 7266
|
||||
231 1544859066 7398
|
||||
232 1544859349 7488
|
||||
233 1544859494 7555
|
||||
234 1544859567 7577
|
||||
235 1544859701 7583
|
||||
236 1544859708 7566
|
||||
237 1544860014 7488
|
||||
238 1544860386 7471
|
||||
239 1544860779 7496
|
||||
240 1544860825 7563
|
||||
241 1544860938 7552
|
||||
242 1544861189 7529
|
||||
243 1544861265 7526
|
||||
244 1544861486 7707
|
||||
245 1544861493 7628
|
||||
246 1544862214 7662
|
||||
247 1544862688 7740
|
||||
248 1544863295 7745
|
||||
249 1544863944 7853
|
||||
250 1544864067 8024
|
||||
251 1544864418 8003
|
||||
252 1544864496 8018
|
||||
253 1544864539 8026
|
||||
254 1544864626 7946
|
||||
255 1544864834 7858
|
||||
256 1544865358 7914
|
||||
257 1544865404 7889
|
||||
258 1544865649 7958
|
||||
259 1544865881 7960
|
||||
260 1544865929 7917
|
||||
261 1544866026 8004
|
||||
262 1544866446 7980
|
||||
263 1544866493 7917
|
||||
264 1544866753 7783
|
||||
265 1544867010 7651
|
||||
266 1544867925 7900
|
||||
267 1544868777 7825
|
||||
268 1544868824 7948
|
||||
269 1544868950 8054
|
||||
270 1544868952 8098
|
||||
271 1544869472 8061
|
||||
272 1544869999 8019
|
||||
273 1544870138 8202
|
||||
274 1544871229 8222
|
||||
275 1544871380 8236
|
||||
276 1544871780 8280
|
||||
277 1544871970 8322
|
||||
278 1544872078 8256
|
||||
279 1544872085 8311
|
||||
280 1544872452 8328
|
||||
281 1544872501 8301
|
||||
282 1544873065 8133
|
||||
283 1544873233 8028
|
||||
284 1544873620 8042
|
||||
285 1544873974 8033
|
||||
286 1544874612 8077
|
||||
287 1544875073 8080
|
||||
288 1544875609 8051
|
||||
289 1544875708 8398
|
||||
290 1544876318 8146
|
||||
291 1544876424 8172
|
||||
292 1544877283 8120
|
||||
293 1544877669 8120
|
||||
294 1544877696 8121
|
||||
295 1544877838 8133
|
||||
296 1544877838 8102
|
||||
297 1544878052 8219
|
||||
298 1544878058 8089
|
||||
299 1544878076 8085
|
||||
300 1544878965 8098
|
||||
301 1544879506 8051
|
||||
302 1544879566 7999
|
||||
303 1544880167 7978
|
||||
304 1544880273 7933
|
||||
305 1544881431 8034
|
||||
306 1544881686 7910
|
||||
307 1544882187 7918
|
||||
308 1544882801 7844
|
||||
309 1544883397 7799
|
||||
310 1544883541 7811
|
||||
311 1544883614 7842
|
||||
312 1544883818 7989
|
||||
313 1544884565 7982
|
||||
314 1544884766 8013
|
||||
315 1544886005 8030
|
||||
316 1544886045 7949
|
||||
317 1544886716 8256
|
||||
318 1544887183 8546
|
||||
319 1544887281 8598
|
||||
320 1544887408 8689
|
||||
321 1544887955 8555
|
||||
322 1544888070 8496
|
||||
323 1544889324 8394
|
||||
324 1544889572 8315
|
||||
325 1544889624 8196
|
||||
326 1544889758 8361
|
||||
327 1544889858 8380
|
||||
328 1544889945 8497
|
||||
329 1544890524 8377
|
||||
330 1544890752 8333
|
||||
331 1544890803 8050
|
||||
332 1544891097 8207
|
||||
333 1544891104 8235
|
||||
334 1544891284 8295
|
||||
335 1544891836 8325
|
||||
336 1544892064 8377
|
||||
337 1544892318 8366
|
||||
338 1544892754 8392
|
||||
339 1544892932 8128
|
||||
340 1544893094 8108
|
||||
341 1544893454 8153
|
||||
342 1544893586 8155
|
||||
343 1544893598 8144
|
||||
344 1544893663 8171
|
||||
345 1544894071 8052
|
||||
346 1544895132 8051
|
||||
347 1544895173 8069
|
||||
348 1544896179 8054
|
||||
349 1544896208 8092
|
||||
350 1544896727 8078
|
||||
351 1544897097 7971
|
||||
352 1544897286 7961
|
||||
353 1544897682 7937
|
||||
354 1544897896 7858
|
||||
355 1544898916 7868
|
||||
356 1544898949 7996
|
||||
357 1544899556 7955
|
||||
358 1544899775 7935
|
||||
359 1544899776 7979
|
||||
360 1544899865 7995
|
||||
361 1544899872 7943
|
||||
362 1544899941 7777
|
||||
363 1544899968 7797
|
||||
364 1544900311 7686
|
||||
365 1544900552 7699
|
||||
366 1544901232 7622
|
||||
367 1544901496 7608
|
||||
368 1544901957 7603
|
||||
369 1544903562 7541
|
||||
370 1544903755 7527
|
||||
371 1544904768 7335
|
||||
372 1544905506 7390
|
||||
373 1544906057 7350
|
||||
374 1544906297 7386
|
||||
375 1544906315 7398
|
||||
376 1544906337 7406
|
||||
377 1544906502 7456
|
||||
378 1544906547 7459
|
||||
379 1544906847 7497
|
||||
380 1544906977 7433
|
||||
381 1544907319 7526
|
||||
382 1544907476 7485
|
||||
383 1544907712 7551
|
||||
384 1544908725 7587
|
||||
385 1544909776 7298
|
||||
386 1544910660 7324
|
||||
387 1544911294 7149
|
||||
388 1544911645 7023
|
||||
389 1544911681 6940
|
||||
390 1544911980 6931
|
||||
391 1544912010 7013
|
||||
392 1544912240 7014
|
||||
393 1544912442 7024
|
||||
394 1544913183 7052
|
||||
395 1544913211 7006
|
||||
396 1544913287 6996
|
||||
397 1544913368 7006
|
||||
398 1544913989 6984
|
||||
399 1544914107 6986
|
||||
400 1544914282 6859
|
||||
401 1544914450 6833
|
||||
402 1544915089 6824
|
||||
403 1544915455 6724
|
||||
404 1544915634 6681
|
||||
405 1544916158 6668
|
||||
406 1544916276 6694
|
||||
407 1544917136 6766
|
||||
408 1544917168 6743
|
||||
409 1544918023 6880
|
||||
410 1544918389 6774
|
||||
411 1544918585 6826
|
||||
412 1544918714 6835
|
||||
413 1544919342 6831
|
||||
414 1544919630 6721
|
||||
415 1544919924 6752
|
||||
416 1544920303 6721
|
||||
417 1544920319 6776
|
||||
418 1544920340 6691
|
||||
419 1544920453 6685
|
||||
420 1544920898 6703
|
||||
421 1544920982 6711
|
||||
422 1544921194 6757
|
||||
423 1544921328 6695
|
||||
424 1544921394 6694
|
||||
425 1544921691 6646
|
||||
426 1544922123 6594
|
||||
427 1544922578 6691
|
||||
428 1544922740 6723
|
||||
429 1544923162 6617
|
||||
430 1544923243 6584
|
||||
431 1544923473 6528
|
||||
432 1544923667 6492
|
||||
433 1544923733 6481
|
||||
434 1544924157 6471
|
||||
435 1544924409 6582
|
||||
436 1544924576 6587
|
||||
437 1544924759 6574
|
||||
438 1544924994 6627
|
||||
439 1544925510 6614
|
||||
440 1544925648 6784
|
||||
441 1544926443 6768
|
||||
442 1544927071 6770
|
||||
443 1544927398 6788
|
||||
444 1544927604 6855
|
||||
445 1544927649 6797
|
||||
446 1544927686 6787
|
||||
447 1544927735 6771
|
||||
448 1544927802 6855
|
||||
449 1544928132 6867
|
||||
450 1544928608 7002
|
||||
451 1544928617 6952
|
||||
452 1544928941 7032
|
||||
453 1544929052 7069
|
||||
454 1544929625 7028
|
||||
455 1544929726 6940
|
||||
456 1544930394 7001
|
||||
457 1544930716 6863
|
||||
458 1544931293 6964
|
||||
459 1544931301 6938
|
||||
460 1544931430 6899
|
||||
461 1544931614 6903
|
||||
462 1544931777 6902
|
||||
463 1544932345 6895
|
||||
464 1544932452 6977
|
||||
465 1544932485 6946
|
||||
466 1544932507 6860
|
||||
467 1544932867 6902
|
||||
468 1544933220 6835
|
||||
469 1544933524 6837
|
||||
470 1544933953 6823
|
||||
471 1544934005 6835
|
||||
472 1544934020 6750
|
||||
473 1544934376 6758
|
||||
474 1544934584 6679
|
||||
475 1544934715 6696
|
||||
476 1544934868 6727
|
||||
477 1544935152 6708
|
||||
478 1544935226 6672
|
||||
479 1544935396 6575
|
||||
480 1544935475 6618
|
||||
481 1544935482 6792
|
||||
482 1544935519 6785
|
||||
483 1544935559 6895
|
||||
484 1544935587 6825
|
||||
485 1544935624 6855
|
||||
486 1544935731 6834
|
||||
487 1544936206 6851
|
||||
488 1544936888 6913
|
||||
489 1544937586 6877
|
||||
490 1544937937 7023
|
||||
491 1544937990 6993
|
||||
492 1544938149 7073
|
||||
493 1544938379 7049
|
||||
494 1544939193 7024
|
||||
495 1544939423 6996
|
||||
496 1544939930 6970
|
||||
497 1544940085 6974
|
||||
498 1544940211 6964
|
||||
499 1544940274 7017
|
||||
500 1544940355 7052
|
||||
501 1544940405 7177
|
||||
502 1544940551 7203
|
||||
503 1544940662 7194
|
||||
504 1544941378 7387
|
||||
505 1544941980 7271
|
||||
506 1544942561 7413
|
||||
507 1544943576 7566
|
||||
508 1544943849 7656
|
||||
509 1544943988 7655
|
||||
510 1544944013 7466
|
||||
511 1544944287 7416
|
||||
512 1544944317 7336
|
||||
513 1544944801 7307
|
||||
514 1544945739 7340
|
||||
515 1544946982 7352
|
||||
516 1544947008 7405
|
||||
517 1544947289 7427
|
||||
518 1544947560 7444
|
||||
519 1544948145 7650
|
||||
520 1544949215 7732
|
||||
521 1544949531 7801
|
||||
522 1544949707 7817
|
||||
523 1544950260 7660
|
||||
524 1544950430 7610
|
||||
525 1544950640 7655
|
||||
526 1544950742 7660
|
||||
527 1544950774 7653
|
||||
@ -0,0 +1,26 @@
|
||||
511 -- 531: elapsed time = 7762s = 129.37% of 6000 target = avg solvetime = 6.47 minutes over 20 blocks
|
||||
491 -- 511: elapsed time = 6297s = 104.95% of 6000 target = avg solvetime = 5.25 minutes over 20 blocks
|
||||
471 -- 491: elapsed time = 3985s = 66.42% of 6000 target = avg solvetime = 3.32 minutes over 20 blocks
|
||||
451 -- 471: elapsed time = 5388s = 89.80% of 6000 target = avg solvetime = 4.49 minutes over 20 blocks
|
||||
431 -- 451: elapsed time = 5144s = 85.73% of 6000 target = avg solvetime = 4.29 minutes over 20 blocks
|
||||
411 -- 431: elapsed time = 4888s = 81.47% of 6000 target = avg solvetime = 4.07 minutes over 20 blocks
|
||||
391 -- 411: elapsed time = 6575s = 109.58% of 6000 target = avg solvetime = 5.48 minutes over 20 blocks
|
||||
371 -- 391: elapsed time = 7242s = 120.70% of 6000 target = avg solvetime = 6.04 minutes over 20 blocks
|
||||
351 -- 371: elapsed time = 7671s = 127.85% of 6000 target = avg solvetime = 6.39 minutes over 20 blocks
|
||||
331 -- 351: elapsed time = 6294s = 104.90% of 6000 target = avg solvetime = 5.25 minutes over 20 blocks
|
||||
311 -- 331: elapsed time = 7189s = 119.82% of 6000 target = avg solvetime = 5.99 minutes over 20 blocks
|
||||
291 -- 311: elapsed time = 7190s = 119.83% of 6000 target = avg solvetime = 5.99 minutes over 20 blocks
|
||||
271 -- 291: elapsed time = 6952s = 115.87% of 6000 target = avg solvetime = 5.79 minutes over 20 blocks
|
||||
251 -- 271: elapsed time = 5054s = 84.23% of 6000 target = avg solvetime = 4.21 minutes over 20 blocks
|
||||
231 -- 251: elapsed time = 5352s = 89.20% of 6000 target = avg solvetime = 4.46 minutes over 20 blocks
|
||||
211 -- 231: elapsed time = 3270s = 54.50% of 6000 target = avg solvetime = 2.73 minutes over 20 blocks
|
||||
191 -- 211: elapsed time = 5190s = 86.50% of 6000 target = avg solvetime = 4.33 minutes over 20 blocks
|
||||
171 -- 191: elapsed time = 8681s = 144.68% of 6000 target = avg solvetime = 7.23 minutes over 20 blocks
|
||||
151 -- 171: elapsed time = 6051s = 100.85% of 6000 target = avg solvetime = 5.04 minutes over 20 blocks
|
||||
131 -- 151: elapsed time = 5256s = 87.60% of 6000 target = avg solvetime = 4.38 minutes over 20 blocks
|
||||
111 -- 131: elapsed time = 5925s = 98.75% of 6000 target = avg solvetime = 4.94 minutes over 20 blocks
|
||||
91 -- 111: elapsed time = 5086s = 84.77% of 6000 target = avg solvetime = 4.24 minutes over 20 blocks
|
||||
71 -- 91: elapsed time = 4811s = 80.18% of 6000 target = avg solvetime = 4.01 minutes over 20 blocks
|
||||
51 -- 71: elapsed time = 7545s = 125.75% of 6000 target = avg solvetime = 6.29 minutes over 20 blocks
|
||||
31 -- 51: elapsed time = 121s = 2.02% of 6000 target = avg solvetime = 0.10 minutes over 20 blocks --- (v12 FORK) ---
|
||||
11 -- 31: elapsed time = 78s = 1.30% of 6000 target = avg solvetime = 0.07 minutes over 20 blocks
|
||||
@ -0,0 +1,10 @@
|
||||
9d47bf4c41b7e8e727e681715acb47fa1677cdba9ca7bcb05ad8cc8abd5daa66 5468697320697320612074657374205468697320697320612074657374205468697320697320612074657374 1806260
|
||||
0d4a495cb844a3ca8ba4edb8e6bcf829ef1c06d9cdea2b62ca46c2a21b8b0a79 4c6f72656d20697073756d20646f6c6f722073697420616d65742c20636f6e73656374657475722061646970697363696e67 1806261
|
||||
a1d6d848b5c5915fccd2f64cf216c6b1a02cf7c77bc80d8d4e51b419e88ff0dd 656c69742c2073656420646f20656975736d6f642074656d706f7220696e6369646964756e74207574206c61626f7265 1806262
|
||||
af3a8544a0221a148c2ac90484b19861e3afca33fe17021efb8ad6496b567915 657420646f6c6f7265206d61676e6120616c697175612e20557420656e696d206164206d696e696d2076656e69616d2c 1806263
|
||||
313399e0963ae8a99dab8af66d343e097dae0c0feb08dbc43ccdafef5515f413 71756973206e6f737472756420657865726369746174696f6e20756c6c616d636f206c61626f726973206e697369 1806264
|
||||
6021c6ef90bff9ae94a7506d623d3a7a86c1756d655f50dd558f716d64622a34 757420616c697175697020657820656120636f6d6d6f646f20636f6e7365717561742e20447569732061757465 1806265
|
||||
2b13000535f3db5f9b9b84a65c4351f386cd2cdedebb8c3ad2eab086e6a3fee5 697275726520646f6c6f7220696e20726570726568656e646572697420696e20766f6c7570746174652076656c6974 1806266
|
||||
fc0e1dad8e895749dc90eb690bc1ba059a1cd772afaaf65a106bf9e5e6b80503 657373652063696c6c756d20646f6c6f726520657520667567696174206e756c6c612070617269617475722e 1806267
|
||||
b60b0afe144deff7d903ed2d5545e77ebe66a3c51fee7016eeb8fee9eb630c0f 4578636570746575722073696e74206f6363616563617420637570696461746174206e6f6e2070726f6964656e742c 1806268
|
||||
64774b27e7d5fec862fc4c0c13ac6bf09123b6f05bb0e4b75c97f379a2b3a679 73756e7420696e2063756c706120717569206f666669636961206465736572756e74206d6f6c6c697420616e696d20696420657374206c61626f72756d2e 1806269
|
||||
@ -1,8 +1,8 @@
|
||||
# Configuration for monerod
|
||||
# Configuration for wownerod
|
||||
# Syntax: any command line option may be specified as 'clioptionname=value'.
|
||||
# Boolean options such as 'no-igd' are specified as 'no-igd=1'.
|
||||
# See 'monerod --help' for all available options.
|
||||
|
||||
data-dir=/var/lib/monero
|
||||
log-file=/var/log/monero/monero.log
|
||||
data-dir=/var/lib/wownero
|
||||
log-file=/var/log/wownero/wownero.log
|
||||
log-level=0
|
||||
@ -1,33 +1,33 @@
|
||||
[Unit]
|
||||
Description=Monero Full Node
|
||||
Description=Wownero Full Node
|
||||
After=network.target
|
||||
|
||||
[Service]
|
||||
User=monero
|
||||
Group=monero
|
||||
User=wownero
|
||||
Group=wownero
|
||||
WorkingDirectory=~
|
||||
RuntimeDirectory=monero
|
||||
RuntimeDirectory=wownero
|
||||
|
||||
# Clearnet config
|
||||
#
|
||||
Type=forking
|
||||
PIDFile=/run/monero/monerod.pid
|
||||
ExecStart=/usr/bin/monerod --config-file /etc/monerod.conf \
|
||||
--detach --pidfile /run/monero/monerod.pid
|
||||
PIDFile=/run/wownero/wownerod.pid
|
||||
ExecStart=/usr/bin/wownerod --config-file /etc/wownerod.conf \
|
||||
--detach --pidfile /run/wownero/wownerod.pid
|
||||
|
||||
# Tor config
|
||||
#
|
||||
## We have to use simple, not forking, because we cannot pass --detach
|
||||
## because stderr/stdout is not available when detached, but torsocks
|
||||
## attempts to write to it, and fails with 'invalid argument', causing
|
||||
## monerod to fail.
|
||||
## wownerod to fail.
|
||||
#Type=simple
|
||||
#Environment=DNS_PUBLIC=tcp
|
||||
## The following is needed only when accessing wallet from a different
|
||||
## host in the LAN, VPN, etc, the RPC must bind to 0.0.0.0, but
|
||||
## by default torsocks only allows binding to localhost.
|
||||
#Environment=TORSOCKS_ALLOW_INBOUND=1
|
||||
#ExecStart=/usr/bin/torsocks /usr/bin/monerod --config-file /etc/monerod.conf \
|
||||
#ExecStart=/usr/bin/torsocks /usr/bin/wownerod --config-file /etc/wownerod.conf \
|
||||
# --non-interactive
|
||||
|
||||
Restart=always
|
||||
Loading…
Reference in new issue